M. BrightSky

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance.

Recent Progress in Phase-Change Memory Technology

We survey progress in the PCM field over the past five years, ranging from large-scale PCM demonstrations to materials improvements for high-temperature retention and faster switching. Both materials and new cell designs that support lower-power switching are discussed, as well as higher reliability for long cycling endurance. Two paths towards higher density are discussed: through 3D integration by the combination of PCM and 3D-capable access devices, and through multiple bits per cell, by understanding and managing resistance drift caused by structural relaxation of the amorphous phase. We also briefly survey work in the nascent field of brain-inspired neuromorphic systems that use PCM to implement non-Von Neumann computing.

NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning

We demonstrate a neuromorphic core with 64k-cell phase change memory (PCM) synaptic array (256 axons by 256 dendrites) with in-situ learning capability. 256 configurable on-chip neuron circuits perform leaky integrate and fire (LIF) and synaptic weight update based on spike-timing dependent plasticity (STDP). 2T-1R PCM unit cell design separates LIF and STDP learning paths, minimizing neuron circuit size. The circuit implementation of STDP learning algorithm along with 2T-1R structure enables both LIF and STDP learning to operate asynchronously and simultaneously within the array, avoiding additional complication and power consumption associated with timing schemes. We show hardware demonstration of in-situ learning with large representational capacity, enabled by large array size and analog synaptic weights of PCM cells.

Sub-30nm scaling and high-speed operation of fully-confined Access-Devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-3] are shown to scale to the <;30nm CDs and <;12nm thicknesses found in advanced technology nodes. Switching speeds at the high (>100uA) currents of NVM writes can reach 15ns; NVM reads at typical (~5uA) current levels can be ≪1usec.

Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-4] are integrated in large (512 × 1024) arrays at 100% yield, and are successfully co-integrated together with Phase Change Memory (PCM). Numerous desirable attributes are demonstrated: the large currents (>;200μA) needed for PCM, the bipolar operation required for high-performance RRAM, the single-target sputter deposition essential for high-volume manufacturing, and the ultra-low leakage ( 10 pA) and high voltage margin (1.5V) needed to enable large crosspoint arrays.

Experimental demonstration of array-level learning with phase change synaptic devices

The computational performance of the biological brain has long attracted significant interest and has led to inspirations in operating principles, algorithms, and architectures for computing and signal processing. In this work, we focus on hardware implementation of brain-like learning in a brain-inspired architecture. We demonstrate, in hardware, that 2-D crossbar arrays of phase change synaptic devices can achieve associative learning and perform pattern recognition. Device and array-level studies using an experimental 10×10 array of phase change synaptic devices have shown that pattern recognition is robust against synaptic resistance variations and large variations can be tolerated by increasing the number of training iterations. Our measurements show that increase in initial variation from 9 % to 60 % causes required training iterations to increase from 1 to 11.

A 256-Mcell Phase-Change Memory Chip Operating at

A fully integrated 256-Mcell multi-level cell (MLC) phase-change memory (PCM) chip in 90-nm CMOS technology is presented. The on-chip circuitry supports fast MLC operation at 4 bit/cell. A programmable digital controller is used to optimize closed-loop gain and timing of the iterative MLC programming scheme and two power-efficient 8-bit DACs support current-controlled as well as voltage-controlled write pulses. The read-out consists of a low-power auto-range frontend followed by a 6-bit cyclic ADC that converts the nonlinear PCM resistance in a range between 10 kΩ and 10 MΩ . A verilog-A model derived from a full 3-D simulation of the PCM cell was developed to simulate the complete chip. The chip was used to demonstrate operation at 2 bit/cell and programming below 10 μs with Ge 2Sb 2Te 5 (GST) based PCM cells at a raw bit error rate of ~ 2 × 10- 4. Two main roadblocks for MLC PCM are drift and endurance. The accuracy of the analog frontend in combination with the programmable controller enables drift mitigation at the system level and the exploration of new materials for MLC operation at 3+ bit/cell.

2{+}

Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3?30? contrast), the operation of large ( 1000?1000 device) arrays at low power tends to require quite large ( 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line?which would eliminate any opportunity for 3D stacking?has been difficult.We review our work at IBM Research?Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1?7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (), a significant voltage margin (over which current nA), and ultra-low leakage ( 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions 30 nm and thicknesses 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low ( 1.2 V) switching voltages, stacking two MIEC devices can support large crossbar arrays for switching voltages up to 2.5 V.

Bit/Cell

Multilevel-cell (MLC) storage is the preferred way for achieving increased capacity and thus lower cost-per-bit in memory technologies. In phase-change memory (PCM), MLC storage is hampered by noise and resistance drift. In this paper the issue of reliability in MLC PCM devices is addressed at the array level. The purpose of this study is to identify the dominant reliability issues in PCM arrays and to provide a practical methodology to assess the reliability and predict the retention of multilevel states. Experimental data are used to derive and fit simple empirical models which can be used to assess the device reliability over the course of time.

MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays

We demonstrate a novel confined PCM cell structure which utilizes a metallic surfactant layer to stabilize the high (and intermediate) resistance state drift in MLC phase change memory technology. The metallic surfactant layer provides an alternative conductive path to the amorphous region during read operation, which makes the cell characteristics immune to amorphous region instabilities such as time- and temperature-dependent resistance drift and noise. The data here focuses on time-dependent drift mitigation. Analytical modeling and numerical simulations show that this cell design can achieve as much as 4× larger resistance ratio between adjacent levels in a 4-level cell. Experimental results confirm its effectiveness as a resistance drift stabilizer, showing ~6× smaller drift coefficient, resulting in a substantially reduced bit error rate.