Hsiang-Lan Lung

Phase-change random access memory: a scalable technology

Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm × 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.

Ultra-Thin Phase-Change Bridge Memory Device Using GeSb

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention

Novel One-Mask Self-Heating Pillar Phase Change Memory

A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900muA at 75nm diameter and multilevel operation are reported

Recent Progress in Phase-Change Memory Technology

We survey progress in the PCM field over the past five years, ranging from large-scale PCM demonstrations to materials improvements for high-temperature retention and faster switching. Both materials and new cell designs that support lower-power switching are discussed, as well as higher reliability for long cycling endurance. Two paths towards higher density are discussed: through 3D integration by the combination of PCM and 3D-capable access devices, and through multiple bits per cell, by understanding and managing resistance drift caused by structural relaxation of the amorphous phase. We also briefly survey work in the nascent field of brain-inspired neuromorphic systems that use PCM to implement non-Von Neumann computing.

Device, circuit and system-level analysis of noise in multi-bit phase-change memory

We present a comprehensive investigation of noise in multi-bit phase-change memory (PCM). The impact of noise on data integrity was quantified with a combination of experiments and simulations. A prototype chip was fabricated to support our system-level analysis, which shows that a raw bit error rate of ∼10−4 is achievable at 3-bit/cell. At the circuit level, we identified the bit line capacitance and the voltage regulator noise as the critical elements determining the electronic readout circuit noise. In addition, device-level measurements showed that 80% of the total noise can be traced back to the fluctuations in the PCM cell current itself. Our analysis captures for the first time how these fluctuations ultimately limit the achievable bit error rate in future multi-level-cell (MLC) PCM chips.

A high performance phase change memory with fast switching speed and high temperature retention by engineering the Ge x Sb y Te z phase change material

Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line and the Ge/Sb2Te3 tie line with the hope of finding a high performance material. Our efforts resulted in a new material that considerably outperforms the conventional GST-225. The switching speed is similar to undoped GST-225, with ∼ 30% lower reset current, and nearly 100°C higher Tx, thus much better thermal stability. The promising properties of this new material are demonstrated in a 128Mb chip and tested both at wafer level and as packaged dies. These devices showed 1E8 cycling endurance and withstood 190 °C testing.

A low power phase change memory using thermally confined TaN/TiN bottom electrode

Application of phase change memory (PCM) has been limited by the high power required to reset the device (changing from crystalline to amorphous state by melting the phase change material). Utilizing the poor thermal and electrical conductivity of TaN we have designed a simple structure that thermally insulates the bottom electrode and thus drastically reduces the heat loss. A 39nm bottom electrode with a TaN thermal barrier and 1.5nm of TiN conductor has demonstrated 30µA reset current, representing a 90% reduction. The benefit of thermal insulation is understood through electrothermal simulation, and the benefit is demonstrated in a 256Mb test chip. The low reset current also improves the reliability and excellent cycling endurance >1E9 is observed. This low power device is promising for expanding the application for PCM.

On the dynamic resistance and reliability of phase change memory

A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this dasiadynamic resistancepsila (Rd) is inversely related to the programming current (I), as Rd = [A/I] + B. While the slope parameter A depends only on the intrinsic properties of the phase change material, the intercept B also depends on the effective physical dimensions of the memory element. We demonstrate that these two parameters provide characterization and insight into the degradation mechanisms of memory cells during operation.

Understanding amorphous states of phase-change memory using Frenkel-Poole model

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

Endurance Improvement of Ge2Sb2Te5-Based Phase Change Memory

We describe a cycling failure mode in Ge 2 Sb 2 Te 5 -based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10 9 cycles.