W. Erven

The second generation of DAQ-Systems at COSY

At the Julich Cooler Synchrotron COSY several experiments are running based on a modular, flexible system design in hardware and software. Future data acquisition experiments should use PC-technologies as far as possible. For the intelligent units initially passive backplanes with Single Bord Computers (SBCs) have been chosen as defined by the PCI Industrial Computer Manufacturing Group (PICMG). For future applications the CompactPCI is considered which combines the IBM PC electrical and software standards with the Eurocard mechanical standards. Connection of the front-end modular systems (CAMAC, VME, FASTBUS) is performed by transparent controllers with PCI compliant interfaces, already available on the market or home made developments. As far as operating systems are concerned UNIX like systems are used. An object oriented, client-server based Experiment Messaging System (EMS) establishes the communication on the application layer between the experiment control, the event builder and different front-end systems. The design criteria for the second generation DAQ-Systems, a first experiment layout, interconnectivity questions and necessary component developments will be described, as well as the problems we have found turning a PC into a diskless system. Important results of performance measurements concerning the DAQ requirements will be given.

The new DAQ system for WASA at COSY

For the operation of the WASA (Wide Angle Shower Apparatus) detector system at the Cooler Synchrotron COSY in Forschungszentrum Julich (FZJ) a new DAQ system has been developed, which conforms to the third generation of the DAQ systems at COSY. This comprises new readout electronics based on an optimized parallel bus with LVDS technology and FPGA-controlled event and buffer management. The new DAQ system has been successfully commissioned in autumn 2006. Further developments aiming at performance optimizations are in progress. The implementation status is presented and performance issues are discussed.

New synchronisation system for experiments at COSY

To improve existing experiments at COSY a new DAQ system is currently under development. It is also well suited to the requirements of WASA at COSY after its transfer from CELSIUS. The DAQ modules are scattered to about 10..20 crates and are able to digitize and store several thousands events before a computer engagement is required. Therefore we need a purely hardware based synchronisation system. The synchronisation system consists of one master module and several output modules housed in a proprietary LVDS crate. It communicates over point to point links with the crate controllers

Development of a High Resolution TDC Module for the WASA Detector System Based on the GPX ASIC

A high resolution time to digital conversion (TDC) module has been developed for the time-stamping of plastics scintillator signals in the WASA detector system. The module is designed in 6U Eurocard form factor for a proprietary optimized backplane bus with LVDS technology. It provides 64 channels and is based on the GPX ASIC from acam-messelectronic gmbh. In the selected mode the GPX has 8 input channels with a resolution up to 81 ps. Design issues and preliminary results of the performance of the module are discussed.

Performance Issues of the New DAQ System for WASA at COSY

For the operation of the WASA (Wide Angle Shower Apparatus) detector system at the Cooler Synchrotron COSY in Forschungszentrum Julich (FZJ) a new DAQ system has been developed, which conforms to the third generation of the DAQ systems at COSY. This comprises new readout electronics based on an optimized parallel bus with LVDS technology and FPGA-controlled event and buffer management. The new DAQ system has been successfully commissioned in autumn 2006. Further developments aiming at performance optimizations are in progress. The implementation status is presented and performance issues are discussed.

An overall MWPC-readout system based on chamber mounted ASIC's

At the Julich Cooler Synchrotron, COSY, the magnetic spectrometer ANKE (Apparatus for Studies of Nucleon and Kaon Ejectils) is installed. Reaction products emitted by an internal target in the forward direction are measured. About 11000 channels are read out. This requirement justified the design of a VLSI based readout system. For this, an analog chip (RAL 118)-a low power high speed eight channel amplifier and discriminator-is used. Digital delay, zero suppression and address encoding are performed by the digital chip RAL 111 from the Rutherford Appleton Laboratory. A scalable and flexible array of chamber mounted front end boards may be adapted to instrument detectors of any size. Readout is performed by serializing hit addresses over a high speed optical link to a CAMAC readout module which serves for additional data reduction, subevent building and a number of test functions. Furthermore, subevent data are transferred using a front panel ECLbus (FERAbus*) to a crate controller with PCI-interface. An industrial PC with diskless UNIX-compatible operating system (NetBSD) is responsible for controlling the CAMAC crate, processing the event data and connecting to a central event builder.

MWPC-readout with the N110 TDC under Linux using a flexible, low-cost FPGA solution

For X-ray spectroscopy at the plasma physics tokamak TEXTOR in Forschungszentrum Julich three N110 TDC modules (developed by Christian Herve, ESRF, Grenoble) are used for the readout of multi-wire proportional counters (MWPC). An optimized low-cost FPGA-based CompactPCI board was developed, that interfaces the N110 and the TEXTOR timing system. The implemented software consists of a Linux device driver and a measurement application program. The Linux device driver is responsible for the transfer of list-mode detector and timing data via DMA into the main memory of a PC. After each TEXTOR shot the application program transfers the data from RAM to disk and adds administrative shot information automatically. Three boards can be read out by one PC simultaneously at the maximum speed of the N110

Development of a readout system for the P̄ANDA Micro Vertex Detector

The Micro Vertex Detector (MVD) is the innermost tracking detector of the ANDA (antiProton Annihilation at Darmstadt) experiment at the upcoming FAIR (Facility for Antiproton and Ion Research) facility in Darmstadt. The detector consists of four barrel and six disk layers of silicon pixel and strip sensors to obtain precise tracking of charged particles. For the development of a front-end ASIC a flexible and powerful readout system was designed to test different ASIC prototypes. We will present the upgrade of the FPGA-based Julich Digital Readout System and measurements of the recent MVD pixel front-end prototype ToPix3. Tests of the implementation of the radiation hard GBT transfer protocol are also shown.

Readout and timing system prototypes for DETNI

Within the DETNI project prototypes of three novel position sensitive thermal neutron detectors types and adequate readout electronics have been developed. The detectors are based on thin solid neutron converters together with two-dimensional readout structures for the detection of secondary particles induced by the neutron capture. They aim at global count rates of up to 100 MHz together with a high spatial and time resolution. In order to utilize these detector characteristics new frontend and data acquisition electronics was required. A novel channel-wise self-triggered ASIC has been developed, which is able to cope with such high count rates and which complies with the signal specifications of the three different detector types. It provides time and analog information of a neutron event with a time resolution of 2 ns. For the data acquisition electronics, which will be described in this paper, prototypes of a clock distribution system and of a FPGA based readout system have been developed with current state-of-the-art electronics. The clock distribution system is to provide high precision, high frequency clock signals to the frontend, which is required to achieve the desired time resolution. The FPGA based readout system is to read out time stamp and analog information of the ASICs, carry out the digitization and transmit the data stream to a host PC

MWPC readout with the GPX ASIC

For X-ray spectroscopy at the plasma physics tokamak TEXTOR in Forschungszentrum Julich a TDC module has been developed for the readout of multi-wire proportional counters (MWPC). The new board comes in CompactPCI form factor and is based on the GPX TDC ASIC from acam messelectronic GmbH. In the selected mode I-mode the GPX has 8 input channels with a typical resolution of 81 ps. The implemented software consists of a Linux device driver and a measurement application program. The Linux device driver is responsible for the transfer of list-mode data via DMA into the main memory of a PC. After each TEXTOR shot the application program transfers the data from RAM to disk and automatically adds administrative shot information.