Axel Ackens

The new DAQ system for WASA at COSY

For the operation of the WASA (Wide Angle Shower Apparatus) detector system at the Cooler Synchrotron COSY in Forschungszentrum Julich (FZJ) a new DAQ system has been developed, which conforms to the third generation of the DAQ systems at COSY. This comprises new readout electronics based on an optimized parallel bus with LVDS technology and FPGA-controlled event and buffer management. The new DAQ system has been successfully commissioned in autumn 2006. Further developments aiming at performance optimizations are in progress. The implementation status is presented and performance issues are discussed.

New synchronisation system for experiments at COSY

To improve existing experiments at COSY a new DAQ system is currently under development. It is also well suited to the requirements of WASA at COSY after its transfer from CELSIUS. The DAQ modules are scattered to about 10..20 crates and are able to digitize and store several thousands events before a computer engagement is required. Therefore we need a purely hardware based synchronisation system. The synchronisation system consists of one master module and several output modules housed in a proprietary LVDS crate. It communicates over point to point links with the crate controllers

Development of a High Resolution TDC Module for the WASA Detector System Based on the GPX ASIC

A high resolution time to digital conversion (TDC) module has been developed for the time-stamping of plastics scintillator signals in the WASA detector system. The module is designed in 6U Eurocard form factor for a proprietary optimized backplane bus with LVDS technology. It provides 64 channels and is based on the GPX ASIC from acam-messelectronic gmbh. In the selected mode the GPX has 8 input channels with a resolution up to 81 ps. Design issues and preliminary results of the performance of the module are discussed.

Performance Issues of the New DAQ System for WASA at COSY

For the operation of the WASA (Wide Angle Shower Apparatus) detector system at the Cooler Synchrotron COSY in Forschungszentrum Julich (FZJ) a new DAQ system has been developed, which conforms to the third generation of the DAQ systems at COSY. This comprises new readout electronics based on an optimized parallel bus with LVDS technology and FPGA-controlled event and buffer management. The new DAQ system has been successfully commissioned in autumn 2006. Further developments aiming at performance optimizations are in progress. The implementation status is presented and performance issues are discussed.

Development of an AMC Module Management Controller

Most functional devices of an ATCA crate contain a controller to handle the management. We designed an AMC board and used a PIC32 for the MMC. Together with the gcc toolchain we chose an open source code as starting point.

MWPC-readout with the N110 TDC under Linux using a flexible, low-cost FPGA solution

For X-ray spectroscopy at the plasma physics tokamak TEXTOR in Forschungszentrum Julich three N110 TDC modules (developed by Christian Herve, ESRF, Grenoble) are used for the readout of multi-wire proportional counters (MWPC). An optimized low-cost FPGA-based CompactPCI board was developed, that interfaces the N110 and the TEXTOR timing system. The implemented software consists of a Linux device driver and a measurement application program. The Linux device driver is responsible for the transfer of list-mode detector and timing data via DMA into the main memory of a PC. After each TEXTOR shot the application program transfers the data from RAM to disk and adds administrative shot information automatically. Three boards can be read out by one PC simultaneously at the maximum speed of the N110

MWPC readout with the GPX ASIC

For X-ray spectroscopy at the plasma physics tokamak TEXTOR in Forschungszentrum Julich a TDC module has been developed for the readout of multi-wire proportional counters (MWPC). The new board comes in CompactPCI form factor and is based on the GPX TDC ASIC from acam messelectronic GmbH. In the selected mode I-mode the GPX has 8 input channels with a typical resolution of 81 ps. The implemented software consists of a Linux device driver and a measurement application program. The Linux device driver is responsible for the transfer of list-mode data via DMA into the main memory of a PC. After each TEXTOR shot the application program transfers the data from RAM to disk and automatically adds administrative shot information.

A compact and flexible CCD readout-system

A compact and flexible low noise control- and readout-system has been developed for a X-ray pnCCD operation. The pnCCD is a new type of CCD originally developed for applications in space for X-ray astronomy. It is designed to perform extremely fast, high resolution spectroscopy of photons in the soft X-ray and infrared region with high efficiency. All interesting parameters of the new readout system like pulse-sequencing and power-up and -down are completely controlled by a front-end system with the help of hardwired interpreters getting their programs from supervising PC. For adaptation of other CCD devices and optimisation, these parameters can be changed interactively by the PC operator. Coupling of the front-end system to the computer is done via a fiber optic link with PCI bus-interface. A menu driven, interactive program system under Linux serves for generation of timing sequences, experiment setup, visualisation and data storage. The system allows an image repetition rate of up to 220 frames/s which is limited only by the pnCCD readout speed.

Concentrator for the readout of the PANDA Micro Vertex Detector based on MicroTCA

The Micro Vertex Detector (MVD) will be used as the central tracking detector in the PANDA (AntiProton Annihilation at Darmstadt) detector system which is under development for the future accelerator facility FAIR in Darmstadt, Germany. The design of the MVD is based on silicon strip detectors at the outer layer and on silicon pixel detectors at the inner layers. Data from the readout ASICs in the front end will be sent via GBT optical links to a multiplexing layer aggregating them to 10 Gbit/s optical uplinks to the Level-1 Trigger network. The multiplexing layer will be based on MTCA.4 using the HGF-AMC, a versatile MTCA.4 module developed by DESY in cooperation with KIT. In order to extend the multiplexing capabilities of the HGF-AMC, a Rear Transition Module (RTM) with 8 optical links has been designed.

Design of an optical uplink with 10 GBit/s between PCIe and MicroTCA

In the context of developments for the PANDA detector system an optical uplink from MicroTCA to PCIe is under development. The uplink is based on X2 transceivers with a nominal speed of 10 GBit/s. The PCIe board has already been produced and it is currently under test. It is based on a Xilinx Virtex 5 (XC5VLX30T) FPGA. For the implementation of the XAUI interface to the X2 transceiver a PM8358 SERDES with a parallel interface to the FPGA is used. The corresponding AMC module is based on the same components. Open issues regarding the FPGA implementation of the link protocol will be discussed.