W. J. Chen

Electrical characteristics of high quality La 2 O 3 gate dielectric with equivalent oxide thickness of 5 /spl Aring/

Electrical and reliability properties of ultrathin La/sub 2/O/sub 3/ gate dielectric have been investigated. The measured capacitance of 33 /spl Aring/ La/sub 2/O/sub 3/ gate dielectric is 7.2 /spl mu/F/cm/sup 2/ that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 /spl Aring/. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm/sup 2/ at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO/sub 2/.

High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ gate dielectrics with equivalent oxide thickness 5-10 /spl Aring/

High quality La/sub 2/O/sub 3/ and Al/sub 2/O/sub 3/ are fabricated with EOT of 4.8 and 9.6 /spl Aring/, leakage current of 0.06 and 0.4 A/cm/sup -2/ and D/sub it/ of both 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, respectively. The high K is further evidenced from high MOSFETs I/sub d/ and g/sub m/ with low I/sub OFF/. Good SILC and Q/sub BD/ are obtained and comparable with SiO/sub 2/. The low EOT is due to the high thermodynamic stability in contact with Si and stable after H/sub 2/ annealing up to 550/spl deg/C.

High-/spl kappa/ Ir/TiTaO/TaN capacitors suitable for analog IC applications

We have developed novel high-/spl kappa/ Ir/TiTaO/TaN capacitors which have high-capacitance density (10.3 fF//spl mu/m/sup 2/), small leakage current at 2 V (1.2/spl times/10/sup -8/ A/cm/sup 2/), and low voltage linearity of the capacitance (89 ppm/V/sup 2/). These excellent results meet the ITRS roadmap requirements for precision analog capacitors for the year 2018. The good performance is due to the very high /spl kappa/ (45) achieved in the TiTaO dielectric and the high work-function (5.2 eV) provided by the Ir electrode.

Thin oxides with in situ native oxide removal [n-MOSFETs]

We have studied the inversion layer mobility of n-MOSFETs with thin-gate oxide of 20 to 70 /spl Aring/. Direct relationship of electron mobility to oxide/channel interface roughness was obtained from measured mobility of MOSFETs and high-resolution TEM. By using a low-pressure oxidation process with native oxide removed in situ prior to oxidation, atomically smooth interface of oxide/channel was observed by high-resolution TEM for oxide thicknesses of 11 and 38 /spl Aring/. The roughness increased to one to two monolayers of Si in a 55-/spl Aring/ oxide. Significant mobility improvement was obtained from these oxides with smoother interface than that from conventional furnace oxidation. Mobility reduction with decreasing oxide thickness was observed in the 20- and 35-/spl Aring/ oxide, with the same atomically smooth oxide/channel interface. This may be due to the remote Coulomb scattering from gate electrode or the gate field variation from poly-gate/oxide interface roughness.

Very high K and high density TiTaO MIM capacitors for analog and RF applications

For the first time, high density (10.3 fF//spl mu/m/sup 2/), low voltage linearity (/spl alpha/=89 ppm/V/sup 2/) and small leakage current (1.2/spl times/10/sup -82/ A/cm/sup 2/ or 5.8 fA/[pF/spl middot/V] at 2V) meet all the ITRS requirements of analog capacitor at year 2018. These are achieved by novel high-K TiTaO (K=45) and high work-function Ir capacitor, which further improve to very high 23 fF//spl mu/m/sup 2/ density and low 81 ppm/V/sup 2/ linearity for higher speed analog/RF ICs at 1GHz, using the fast /spl alpha/ decay mechanism with increasing frequency.

Formation of Ni germano-silicide on single crystalline Si/sub 0.3/Ge/sub 0.7//Si

We have studied the Ni and Co germano-silicide on Si/sub 0.3/Ge/sub 0.7//Si. The Ni germano-silicide shows a low sheet resistance of 4-6 /spl Omega///spl square/on both P/sup +/N and N/sup +/P junctions, which is much smaller than Co germano-silicide. In addition, small junction leakage currents of 3/spl times/10/sup -8/ A/cm/sup 2/ and 2/spl times/10/sup -7/ A/cm/sup 2/ are obtained for Ni germano-silicide on P/sup +/N and N/sup +/P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.

Fully silicided NiSi and germanided NiGe dual gates on SiO 2 n- and p-MOSFETs

We have fabricated the fully silicided NiSi and germanided NiGe dual gates n- and p-MOSFETs on 1.9 nm thick SiO/sub 2/ gate dielectric. The extracted work functions of fully NiSi and NiGe gates from thickness-dependent flat band voltage were 4.55 and 5.2 eV respectively, which may provide possible wide work function tuning using NiSi/sub t-x/Ge/sub x/. In additional to the lower gate current than Al gate n- and p-MOSFETs, the fully silicided NiSi and germanided NiGe gates MOSFETs show electron and hole mobilities close to universal mobility values with special advantage of process compatible to current VLSI fabrication line.

The effect of native oxide on epitaxial SiGe from deposited amorphous Ge on Si

We have investigated the effect of native oxide on the epitaxial SiGe from deposited amorphous Ge on Si. Instead of epitaxial growth by molecular beam epitaxy or ultrahigh-vacuum chemical vapor deposition, the SiGe layer is formed by this simple process followed by an annealing step. As observed by transmission electron microscopy, the suppression of native oxide plays an important role to achieve epitaxial SiGe. The SiGe quality degrades with increasing native oxide thickness and becomes polycrystalline with a ∼20 A interfacial native oxide. On the other hand, single crystalline SiGe can be routinely formed from a HF-vapor treated Si surface.

Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/

We report a very simple process to fabricate Al/sub 2/O/sub 3/ gate dielectric for CMOS technology with k (9.0 to 9.8) greater than Si/sub 3/N/sub 4/. Al/sub 2/O/sub 3/ is formed by direct oxidation from thermally evaporated Al. The 48 /spl Aring/ Al/sub 2/O/sub 3/ has /spl sim/7 orders lower leakage current than equivalent 21 /spl Aring/ SiO/sub 2/. A good Al/sub 2/O/sub 3/-Si interface was evidenced by the low interface density of 1/spl times/10/sup 11/ eVcm/sup -2/ and compatible electron mobility with thermal SiO/sub 2/. Good reliability is measured from the small stress induced leakage current (SILC) after 2.5 V stress for 10,000 s.

The effect of native oxide on thin gate oxide integrity

We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using HF-vapor treated and H/sub 2/ baked processes. Furthermore, an extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm/sup 2/ and a large charge injection of 7.9/spl times/10/sup 4/ C/cm/sup 2/. The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole traps.