Yung-Hsien Wu

High density metal-insulator-metal capacitor based on ZrO2∕Al2O3∕ZrO2 laminate dielectric

The metal-insulator-metal (MIM) capacitor for analog and rf applications has been developed with ZrO2∕Al2O3∕ZrO2 laminate as the dielectric. The high capacitance density of 21.54fF∕μm2 can be achieved due to the tetragonal ZrO2 which makes the higher dielectric constant of 38.7. This MIM capacitor also demonstrates the quadratic voltage coefficient of 2443ppm∕V2 and the good leakage current of 2.11×10−6A∕cm2 at 2V which is ascribed to the inserted Al2O3. Since the Schottky emission is suggested as the major dielectric conduction mechanism, a further reduced quadratic voltage coefficient and leakage characteristic can be realized by using a high work-function electrode. The combination of the promising electrical properties and the desirable process integration renders this structure highly suitable for advanced MIM capacitors.

Fabrication of very high resistivity Si with low loss and cross talk

We have used proton and As/sup +/ implantation to increase the resistivity of conventional Si (10 /spl Omega/-cm) and Si-on-quartz substrates, respectively. A high resistivity of 1.6 M/spl Omega/-cm is measured that is close to intrinsic Si and semi-insulating GaAs. Very low loss and cross coupling of 6.3 dB/cm and -79 dB/cm (10 /spl mu/m gap) at 20 GHz are measured on these samples, respectively. The very high resistivity and improved rf performance are due to the extremely fast /spl sim/1 ps carrier lifetime stable even after a 400/spl deg/C annealing for 1 h. Little negative effect on gate oxide integrity is also observed as evidenced by the comparable stress-induced leakage current and charge-to-breakdown for 30 /spl Aring/ oxides.

Nitrided Tetragonal

Employment of a tetragonal ZrO2 film as the charge-trapping layer for nonvolatile memory was investigated and the NH3 nitridation effect of the ZrO2 film on memory performance was also explored in this letter. The permittivity of the tetragonal ZrO2 film is slightly reduced from 38.7 to 36.9 after nitridation; nevertheless, nitridation introduces more trapping sites and passivates the grain boundary channel which results in a high operation speed in terms of 2.6-V flatband voltage shift by programming at +10 V for 10 ms and a good retention characteristic with 20.2% charge loss after ten-year operation at 125degC, both are superior to that without NH3 nitridation. Most importantly, the process is fully compatible with existent ULSI technology and paves the way to adopt a high-permittivity crystalline dielectric as the charge-trapping layer for future high-performance nonvolatile memory.

\hbox{ZrO}_{2}

The measured RF performance of 0.5, 0.25, and 0.18 /spl mu/m MOSFETs gradually saturates as scaling down occurs, which can be explained by the derived analytical equation and simulation. The source-drain overlap capacitance, C/sub gd/, and non-quasi-static effect are the main factors but scale much slower than L/sub g/.

as the Charge-Trapping Layer for Nonvolatile Memory Application

Using nanocrystal (nc) TiO₂ and TaON buffer layer, the Ni/GeO_x/nc-TiO₂/TaON/TaN resistive random access memory (RRAM) showed forming-free resistive switching, self compliance set/reset currents, excellent current distribution, low 0.7-pJ switching energy, and long 10¹⁰ cycling endurance. The very long endurance in this novel RRAM may create new applications beyond Flash memory.

The performance limiting factors as RF MOSFETs scale down

A Ge-stabilized tetragonal ZrO2 dielectric with a permittivity (κ) value of 36.5 has been obtained by annealing a ZrO2/Ge/ZrO2 laminate at 500 °C and it is a more reliable approach toward stabilizing a tetragonal ZrO2 film. However, metal-insulator-metal (MIM) capacitors with the sole tetragonal ZrO2 film as an insulator achieve a high capacitance density of 27.8 fF/μm2 at the price of a degraded quadratic voltage coefficient of capacitance (VCC) of 81 129 ppm/V2 and unacceptably high leakage current. By capping an amorphous La-doped ZrO2 layer with a κ value of 26.3 to block grain boundaries-induced leakage paths of the crystalline ZrO2 dielectric, high-performance MIM capacitors in terms of a capacitance density of 19.8 fF/μm2, a VCC of 3135 ppm/V2, leakage current of 6.5×10−8 A/cm2 at −1 V, as well as a satisfactory capacitance change of 1.21% after ten-year operation can be realized.

Long-Endurance Nanocrystal

We have investigated the effect of native oxide on the epitaxial SiGe from deposited amorphous Ge on Si. Instead of epitaxial growth by molecular beam epitaxy or ultrahigh-vacuum chemical vapor deposition, the SiGe layer is formed by this simple process followed by an annealing step. As observed by transmission electron microscopy, the suppression of native oxide plays an important role to achieve epitaxial SiGe. The SiGe quality degrades with increasing native oxide thickness and becomes polycrystalline with a ∼20 A interfacial native oxide. On the other hand, single crystalline SiGe can be routinely formed from a HF-vapor treated Si surface.

\hbox{TiO}_{2}

CF4 plasma treatment on germanium (Ge) surface is proposed in this work to alleviate the strong Fermi level pinning between metal/Ge, and its effectiveness is also explored for n- and p-type Ge wafers. It is found that samples with CF4 plasma treatment reveal conduction behavior transition between Schottky and ohmic characteristics, a metal-work-function-dependent Schottky barrier height as well as modulated contact resistance, and these results confirm the depinning of Fermi level. This depinning can be explained by the effective capability in passivating dangling bonds at Ge surface through fluorine atoms and the formation of Ge-F binding with partial ionic property, both of which are helpful in decreasing the number of surface states and consequently release the pinning effect.

Resistive Memory Using a TaON Buffer Layer

We have used a simple process to fabricate Si/sub 0.3/Ge/sub 0.7//Si p-MOSFETs. The Si/sub 0.3/Ge/sub 0.7/ is formed using deposited Ge followed by 950/spl deg/C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm/sup 2//Vs is obtained from the Si/sub 0.3/Ge/sub 0.7/ p-MOSFET that is /spl sim/two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 /spl Aring/ Si/sub 0.3/Ge/sub 0.7/ thermal oxide grown at 1000/spl deg/C has a high breakdown field of 15 MV/cm, low interface trap density (D/sub it/) of 1.5/spl times/10/sup 11/ eV/sup -1/ cm/sup -2/, and low oxide charge of 7.2/spl times/10/sup 10/ cm/sup -2/. The source-drain junction leakage after implantation and 950/spl deg/C RTA is also comparable with the Si counterpart.

High-performance metal-insulator-metal capacitor with Ge-stabilized tetragonal ZrO2/amorphous La-doped ZrO2 dielectric

A Ge-stabilized tetragonal ZrO2 (t-ZrO2) film formed by incorporating Ge atoms thermally driven from an underlying Ge layer into a ZrO2 film was investigated as the gate dielectric for Ge metal-oxide-semiconductor (MOS) capacitors fabricated on a Si substrate. A sole t-ZrO2 film on Ge is not eligible for the gate dielectric because of the poor interface quality. By using a thermally-grown ultrathin GeO2 film as an interfacial layer, the t-ZrO2/GeO2/Ge stack shows improved interface characteristics and a permittivity (κ) value of 36.6 for the t-ZrO2. In addition, the stack also demonstrates good leakage current since the amorphous GeO2 layer terminates grain boundary channels in the crystalline ZrO2. Further leakage current suppression can be achieved by a H2 annealing of the t-ZrO2/GeO2/Ge stack since the defects at grain boundaries can be effectively passivated, which makes a leakage current of 1.08×10−6 A/cm2 at VFB−1 V for effective oxide thickness of 1.66 nm and paves an alternative avenue to develop ...