W. K. Choi

Synthesis of Silicon Nanowires and Nanofin Arrays Using Interference Lithography and Catalytic Etching

We report results on the synthesis of silicon nanostructures that were fabricated using a combination of interference lithography and catalytic etching. With this technique, we were able to create nanostructures that are perfectly periodic over very large areas (1 cm(2) or more), where the cross-sectional shapes and the array ordering can be varied. Furthermore this technique can readily and independently control the sizes and spacings of the nanostructures down to spacings of 200 nm or less. These characteristics cannot be achieved using other known techniques.

Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal–insulator– semiconductor structure

The memory effect of a trilayer structure (rapid thermal oxide/Ge nanocrystals in SiO2/sputtered SiO2) was investigated via capacitance versus voltage (C–V) measurements. The Ge nanocrystals were synthesized by rapid thermal annealing of the cosputtered Ge+SiO2 films. The memory effect was manifested by the hysteresis in the C–V curve. Transmission electron microscope and C–V results indicated that the hysteresis was due to Ge nanocrystals in the middle layer of the trilayer structure.

A high performance MIM capacitor using HfO 2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO/sub 2/ high-/spl kappa/ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (/spl sim/200/spl deg/C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO/sub 2/ MIM capacitor can provide a higher capacitance density than Si/sub 3/N/sub 4/ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2/spl times/10/sup -9/ A/cm/sup 2/ at 3 V is achieved. All of these make the HfO/sub 2/ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications.

Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation

The charge storage and program/erase mechanisms in polysilicon-oxide-nitride-oxide-silicon (SONOS) memory structures with charge-storage layers of different materials are investigated in this paper. In particular, the use of a HfAlO charge-storage layer in a SONOS-type memory structure is proposed. Compared to other high-/spl kappa/ charge-storage layers, HfAlO has the advantage of high-speed program/erase of HfO/sub 2/ as well as the good charge-retention time of Al/sub 2/O/sub 3/, which makes HfAlO a promising candidate for the charge-storage layer in a SONOS-type memory. The use of HfAlO with different HfO/sub 2/ and Al/sub 2/O/sub 3/ compositions as a blocking-oxide layer in SONOS-type structures is also investigated.

Infrared and x-ray photoelectron spectroscopy studies of as-prepared and furnace-annealed radio-frequency sputtered amorphous silicon carbide films

The effects of annealing on the structural properties of radio-frequency sputtered amorphous silicon carbide films prepared under different hydrogen partial pressures (PH) were investigated. Infrared (IR) results of the as-prepared films suggest that as PH increases, more hydrogen is incorporated into the film to form the Si–H and C–H bonds and less silicon and carbon atoms are available to form the Si–C bonds. X-ray photoelectron spectroscopy (XPS) results of the as-prepared films agree with the IR results in that the percent of Si–C decreases and the percent of Si–H and C–H increases as PH increases. IR and XPS results of the annealed films suggest that as the annealing temperature increases, the dangling Si and C bonds will combine to form the Si–C bonds for the unhydrogenated samples. The increase in Si–C bonds for the hydrogenated samples is more likely to be due to the formation of Si–C bonds from the breaking up of the Si–H and C–H bonds.

TMAH etching of silicon and the interaction of etching parameters

Abstract A study of tetramethylammonium hydroxide (TMAH) etching of silicon and the interaction of etching parameters has been carried out. We find that the silicon etch rate increases as the TMAH concentration increases and it reaches a maximum at 4 wt.%. The etch rate of n-type silicon is found to be slightly higher than that of p-type silicon. We conclude that illumination has no effect on the etch rate with our present experimental set-up. Etching experiments on silicon oxide layers show that both wet and dry oxides etch faster in lower TMAH concentration, and wet oxide generally etches faster than a dry oxide layer. A higher temperature also results in a higher etch rate for both the wet and dry oxides. From factorial analysis, we conclude that for silicon etching, the interaction between TMAH concentration and substrate type is the strongest. The silicon oxide etching experiments show that temperature is the most prominent factor and the most pronounced interaction exists between temperature and TMAH concentration.

Raman characterization of germanium nanocrystals in amorphous silicon oxide films synthesized by rapid thermal annealing

Raman characterization of germanium (Ge) nanocrystals embedded in amorphous silicon oxide (a-SiO2) films synthesized by rapid thermal annealing (RTA) has been carried out. The samples were prepared by cosputtering Ge and SiO2 targets using a rf magnetron sputtering machine. Ge nanocrystals can only be obtained from samples sputtered with six pieces of Ge attached to the SiO2 target. For samples annealed at different RTA temperatures, the Raman spectra indicated a transition from amorphous to nanocrystalline Ge when annealed between 600 and 750 °C. The spectra were analyzed in terms of phonon confinement model and the estimated nanocrystal size was between 20 and 66 A. A minimum annealing time of 160 s at 750 °C was necessary for Ge nanocrystal formation. Strong visible broadband photoluminescence was observed from the nanocrystals and the photoluminescence showed a blueshift with decrease in the nanocrystal size. The effect of compressive stress on nanocrystal growth was examined by varying the rampup and...

Physical and electrical characterization of HfO2 metal–insulator–metal capacitors for Si analog circuit applications

Thin films of HfO2 high-k dielectric have been prepared by pulsed-laser deposition at various substrate temperatures and pressures. X-ray diffraction, atomic force microscopy, secondary ion mass spectroscopy and ellipsometry were used to characterize the deposited films. Experimental results show that substrate temperature has little effect on the stoichiometry, while deposition pressure plays an important role in determining the ratio of Hf and O. It is also found that the optical properties of the HfO2 thin films have strong dependence on both the deposition temperature and pressure. The electrical properties of HfO2 metal–insulator–metal (MIM) capacitors were investigated at various deposition temperatures. It is shown that the HfO2 (56 nm) MIM capacitor fabricated at 200 °C shows an overall high performance, such as a high capacitance density of ∼3.0 fF/μm2, a low leakage current of 2×10−9 A/cm2 at 3 V, low-voltage coefficients of capacitance, and good-frequency dispersion properties. All of these ind...

Crystalline zirconia oxide on silicon as alternative gate dielectrics

Epitaxial crystalline yittria-stabilized zirconia (YSZ) oxide films were grown on silicon wafers by the laser molecular beam epitaxy technique. The interface of crystalline YSZ film in contact with silicon was found to be atomically sharp and commensurately crystallized without an amorphous layer. An x-ray photoelectron spectroscopy depth profile and transmission electron microscopy investigation showed that no SiO2 formed at the interface. For a film with electrical equivalent oxide thickness (teox) 14.6 A, the leakage current is about 1.1×10−3 A/cm2 at 1 V bias voltage. The hysteresis and interface state density in this film are measured to be less than 10 mV and 2.0×1011 eV−1 cm−2, respectively.

Effect of current direction on the lifetime of different levels of Cu dual-damascene metallization

Electromigration in the lower metal (M1) and the upper metal (M2) of Cu dual-damascene interconnections has been studied. The failure times of M2 test structures are significantly longer than those of identical M1 structures. It is proposed that this asymmetry is the result of a difference in the location of void formation and growth, which is believed to be related to the ease of electromigration-induced void nucleation and growth at the Cu/Si3N4 interface. Asymmetric via reliability is therefore an intrinsic characteristic of current Cu interconnect technology.