V. Ho

Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal–insulator– semiconductor structure

The memory effect of a trilayer structure (rapid thermal oxide/Ge nanocrystals in SiO2/sputtered SiO2) was investigated via capacitance versus voltage (C–V) measurements. The Ge nanocrystals were synthesized by rapid thermal annealing of the cosputtered Ge+SiO2 films. The memory effect was manifested by the hysteresis in the C–V curve. Transmission electron microscope and C–V results indicated that the hysteresis was due to Ge nanocrystals in the middle layer of the trilayer structure.

Germanium diffusion and nanocrystal formation in silicon oxide on silicon substrate under rapid thermal annealing

The effect of rapid thermal annealing temperature on the diffusion of silicon (Si) and germanium (Ge) and the formation of Ge nanocrystals in a silicon oxide matrix was investigated. The formation of Ge nanocrystals was attributed mainly to the reduction of Ge suboxides by Si diffused from the Si substrate. For samples annealed at 800°C, the nanocrystals were uniform in size and distributed evenly in the bulk of the oxide but became denser nearer to the silicon–silicon oxide (Si–SiO2) interface. When the sample was annealed at 900°C, two regions with different nanocrystal densities and size distributions separated by a region void of nanocrystals were observed. The region of denser nanocrystals was located near the Si–SiO2 interface. For annealing at 1000°C, nanocrystals were only observed at the Si–SiO2 interface and these have significant size variation, with the rest of the oxide being void of nanocrystals. The nanocrystals formed at 900 and 1000°C were generally found to be defective.

Minimization of germanium penetration, nanocrystal formation, charge storage, and retention in a trilayer memory structure with silicon nitride/hafnium dioxide stack as the tunnel dielectric

Trilayer structures, consisting of a rapid thermal oxide (RTO) layer (2.5 or 5 nm thick) grown on silicon, a sputtered Ge middle layer (3–20 nm thick), and a 50-nm-thick sputtered silicon oxide capping layer, exhibit significant penetration of Ge atoms into the silicon substrate for devices with the smaller (2.5 nm) RTO thickness, resulting in negligible nanocrystal formation and hence no charge storage or memory effect. The Ge penetration is minimized by replacing the RTO layer with a high dielectric constant (high-κ) silicon nitride/hafnium dioxide stack (grown by metalorganic chemical vapor deposition) having a larger physical thickness but smaller equivalent oxide thickness of 1.9 nm. Results show that the high-κ trilayer structure exhibits better charge storage capability (in terms of a lower program voltage) and better charge retention performance as compared to the RTO trilayer structure.

Effect of germanium concentration and tunnel oxide thickness on nanocrystal formation and charge storage/retention characteristics of a trilayer memory structure

The effect of germanium concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal–insulator–semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO2 cosputtered middle layer (i.e., lower Ge concentration), even though a higher charge storage capability was obtained from devices with a thinner RTO layer, the charge retention capability was poorer as compared to devices with a thicker RTO layer.

Effects of rapid thermal annealing time and ambient temperature on the charge storage capability of SiO 2 /pure Ge/rapid thermal oxide memory structure

A metal-insulator-semiconductor device with a tri-layer structure consisting of sputtered silicon dioxide (SiO2) (∼ 50 nm)-evaporated pure germanium (Ge) (2.3 nm)-rapid thermal oxidation (RTO) oxide (5 nm) was fabricated on a p-type silicon (Si) substrate. This structure was rapid thermal annealed at 1000 °C in argon. For the as-prepared structure and those that were annealed from 10 to 400 s, it was observed that the hysteresis of the capacitance versus voltage (C-V) curves increased from ∼ 1.5 to 10 V. This indicated that the charge storage capability of the structure improved with increasing annealing time. From our transmission electron microscope results, we observed that as the annealing time increased, more Ge nanocrystals were formed. When the ambient temperature was increased from 25 to 150 °C, the width of the hysteresis of our devices reduced. The charge storage mechanism of the Ge nanocrystals was explained in terms of charging/discharging from traps at the internal/surface of Ge nanocrystals and tunneling of charges to the interface states at the Si-RTO oxide interface.

Electrical characterization of a trilayer germanium nanocrystal memory device

In this paper, we report the effects of the thickness of the middle layer and the rapid thermal oxide (RTO) layer on the charge storage capability of the trilayer devices. The capacitance versus voltage (C-V) measurements showed that devices with a thinner middle layer and the same thickness for the RTO layer have better charge storage capability (i.e., larger C-V hysteresis). For devices with the same middle layer thickness, a larger C-V hysteresis was observed from devices with a thinner RTO layer.

Switching from ⟨110⟩ to ⟨100⟩ orientation increases both the on current and off current of p-channel metal-oxide semiconductor transistors

If the on current of p-channel metal-oxide semiconductor (PMOS) transistors fabricated on (100) silicon substrate can be easily increased by switching from ⟨110⟩ to ⟨100⟩ orientation because of faster hole transport in the “on state,” it is natural to expect that this switching can also increase the off current because of faster hole transport in the “off state.” Indeed we managed to observe this experimentally for relatively long PMOS transistors. In this letter, we will also show that there is an overall performance improvement in PMOS transistors despite the increase in both on current and off current.

Reduced boron lateral ion channeling in very short p-channel transistors by switching from ⟨110⟩ to ⟨100⟩ channel orientation

The on-current of p-channel transistors fabricated on (100) Si substrate can be easily increased by switching from ⟨110⟩ to ⟨100⟩ channel orientation because of faster hole transport. In this paper, we pointed out that there is also a reduction in the gate-to-source/drain overlap, resulting in an increase in the effective channel length for p-channel transistors. Our experimental observation can be explained by a reduction in boron lateral ion channeling due to this switch.

Effect of tensile stress on the various components of the off current of n-channel metal-oxide-semiconductor transistors

The authors found that tensile stress actually slightly increases the on current and the subthreshold off current but it slightly decreases the gate leakage current and the drain junction leakage current for n-channel metal-oxide-semiconductor transistors. For short transistors, the subthreshold off current dominates over the other two components of the off current such that tensile stress slightly increases both the on current and the off current. However, in the on current versus the logarithm of off current plot, tensile stress increases the on current for a constant off current such that the overall effect of tensile stress is an improvement.