W. Rhett Davis

Design and CAD for 3D integrated circuits

High density through silicon vias (TSV) can be used to build 3DICs that enable unique applications in computing, signal processing and memory intensive systems. This paper presents several case studies that are uniquely enhanced through 3D implementation, including a 3D CAM, an FFT processor, and a SAR processor. The CAD flow used to implement for these designs is described. 3DIC requires higher fidelity thermal modeling than 2DIC design. The rationale for this requirement is established and a possible solution is presented.

Exploring compromises among timing, power and temperature in three-dimensional integrated circuits

Three-dimensional integrated circuits (3DICs) have the potential to reduce interconnect lengths and improve digital system performance. However, heat removal is more difficult in 3DICs, and the higher temperatures increase delay and leakage power, potentially negating the performance improvement. Thermal vias can help to remove heat, but they create routing congestion, which also leads to longer interconnects. It is therefore very difficult to tell whether or not a particular system may benefit from 3D integration. In order to help understand this trade-off, physical design experiments were performed on a low-power and a high-performance design in an existing 3DIC technology. Each design was partitioned and routed with varying numbers of tiers and thermal-via densities. A thermal-analysis methodology is developed to predict the final performance. Results show that the lowest energy per operation and delay are achieved with 4 or 5 tiers. These results show a reduction in energy and delay of up to 27% and 20% compared to a traditional 2DIC approach. In addition, it is shown that thermal-vias offer no performance benefit for the low-power system and only marginal benefit for the high-performance system

FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology

This paper discusses design rules and layout guidelines for an open source predictive process design kit (PDK) for multi-gate 15nm FinFET devices. Additional design rules are introduced considering process variability, and challenges involved in fabrication beyond 20nm. Particularly, double patterning lithography is assumed and a unique set of design rules are developed for critical dimensions. In order to improve the FinFET layout density, Middle-of-line local interconnect layers are implemented for the FinFET layout. The rules are further validated by running Calibre design-rule checks on Virtuoso layout of an Inverter and NAND4 cells. As part of the validation process, the area of a FreePDK15 inverter was compared to the area of an inverter in 45nm bulk MOS process and the ratio was found to be 1:6. This kit primarily aims to support introduction of sub-20nm FinFET devices into research and universities.

Rationale for a 3D heterogeneous multi-core processor

Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior.

An architecture for energy efficient sphere decoding

Sphere decoding has become a popular implementation of MIMO detection due to its improved performance at lower hardware complexity. ASIC implementations have proven the feasibility of this method but fail to effectively address the issue of power efficiency. In this work, we propose an improved architecture that aims to exploit a combination of a deeper pipeline and the use of single-port read and write memories to increase the energy efficiency (bits/sec/mW) of the implementation. We see a 30% and 80% increase in memory and logic energy efficiencies when compared to an unpipelined version of the implementation in 0.18 mu technology.

Automated Design Space Exploration for DSP Applications

We present a performance analysis framework that efficiently generates and analyzes hardware designs for computationally intensive signal processing applications. Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation. Cost functions provided by our framework allow the user to reduce the design space to a set of efficient hardware implementations that meet performance constraints. We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold. This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs. Our work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. We illustrate the efficiency and accuracy of our framework by generating finite impulse response filter structures used in several signal processing applications such as adaptive equalizers and quadrature mirror filters. The results show that hardware filter structures generated by our framework can achieve, on average, a 3 fold increase in power efficiency when compared to manually constructed designs.

Pathfinder 3D: A flow for system-level design space exploration

Three dimensional integration technology has the potential to provide enhanced performance and device density gains beyond that available from technology scaling alone. However, it provides plethora of design choices for system designers. The full exploitation of the benefits of 3D integration requires a system-level exploration flow which can facilitate in finding an optimal 3D design by comparing possible early design choices. In this paper we present a flow for fast system-level exploration useful for path finding studies. The flow enables users to explore the tradeoff between different stacking and partitioning schemes in terms of performance, power, and temperature. We also present a free open source design kit compiler, FreePDK3D45 and a tool for fast floorplan evaluation of TSV-based digital architectures, Pathfinder3D. The open source design kit and architecture evaluator can help the community to research, learn and explore the various aspects of 3D integration. Using the proposed flow and design kit, we present a case study of 3D integration of a Network on Chip. This case study demonstrates system-level comparisons of the performance, power and temperature of different homogenously partitioned stacking schemes.

Compact Electrothermal Modeling of an X-band MMIC

Compact electrothermal modeling of lumped electrical devices and compact thermal modeling of volumetric materials enables efficient electrothermal modeling of microwave circuits. The compact thermal model of the body of an X-band MMIC is based on analytical solutions of the heat diffusion equation in thermal sub-volumes. The model is accurate and captures thermal nonlinearities. The model considers complex MMIC features such as surface metallization and vias, as well as the mounting configurations including lead-frame, carrier, and printed circuit board. This is coupled with electrothermal models of transistors and of resistors. The models are incorporated in a multi-physics simulator that uses the same model in both transient and harmonic analysis of an X-band LNA MMIC. Simulations are validated with steady-state thermal measurements

Thermal Pathfinding for 3-D ICs

System architects traditionally use high-level models of component blocks to predict trends for various design metrics. However, with continually increasing design complexity and a confusing array of manufacturing choices, system-level design decisions cannot be made without considering physical-level details. This effect is more pronounced for 3-D integrated circuits (ICs) because it provides a plethora of physical-level design choices, such as the number of stacking layers and the type of 3-D bonding method, along with the choices provided by 2-D ICs. Thus, it is necessary for system-level flows to predict the complex interactions among system performance, power, temperature, floorplanning, process technology, computer architecture, and software/workloads. This is often called pathfinding. This paper presents a pathfinding flow that integrates SystemC transaction-level electrical and dynamic thermal simulations. The goal of this flow is to pass complex physical constraints to system architects in a convenient form. The applicability of the proposed flow is shown using an example stacking of two processor cores and L2 cache in two-tier 3-D stack.

Automated Architectural Exploration for Signal Processing Algorithms

This paper presents a design environment for efficiently generating application-specific intellectual property (IP) cores for system level signal processing algorithms. We present our view of a framework that combines common electronic design automation (EDA) tools to alleviate the designer from manually constructing the hardware models and analyzing their performance. We use our framework to efficiently implement design optimizations that improve the performance of the overall hardware architectures. Our framework is well suited for designers with a range of signal processing and hardware expertise. Our framework generates the dedicated IP cores and estimates the performance such as area, critical path delay, and latency within seconds. Parts of our framework also compare different hardware designs for various digital signal processing (DSP) algorithms and allows the designer to make architectural decisions earlier in the hardware design process. We use a GUI-based framework invoked from MATLAB to automatically build and analyze the hardware designs. Our framework generates efficient hardware designs described in SystemC and Verilog code, along with the performance metrics for each architecture. We illustrate the use of our framework by exploring and analyzing architectural variations of two case studies: finite impulse response (FIR) filters and adaptive channel equalizers