D.S. Wills

On-chip decoupling capacitor optimization using architectural level prediction

Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular technique to counter this issue involves the usage of decoupling capacitors. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on activity signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of the proposed technique on typical microprocessor implementations (the Alpha 21264 and the Pentium II) indicates that this technique can produce up to a 30% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.

A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001

GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits.

An architectural solution for the inductive noise problem due to clock-gating

As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. However, it introduces inductive noise that can limit voltage scaling. This paper introduces an architectural approach for reducing inductive noise due to clock-gating through gradual activation/deactivation of units. This technique provides a 2/spl times/ reduction in ground bounce on a 16 bit ALU simulated in SPICE, while reducing simulated SPEC95 performance by less than 5% on a typical superscalar architecture.

Heterogeneous architecture models for interconnect-motivated system design

On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rents rule-based wiring models. These architecture models allow flexible heterogeneous system specifications, enabling investigations of prospective designs in different technology scenarios. Comparisons against actual data demonstrate the models effectiveness for architecture explorations with highly accurate estimations of local and global wiring demand, as well as chip area and cycle time. Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for future architectures.

Inductive noise reduction at the architectural level

A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach gigascale integration, chip power consumption is becoming a critical system parameter Deactivating idle units provides needed reductions in power consumption. However it introduces inductive noise that can limit voltage scaling. The paper introduces an architectural approach for reducing this inductive noise by providing gradual activation and deactivation of functional blocks. This technique provides a 2/spl times/ reduction in ground bounce current on a 16 bit ALU simulated in SPICE, while reducing simulated SPEC95 performance by less than 5% on a typical superscalar architecture. It has also been demonstrated to be effective for image processing SIMD architectures.

On-chip decoupling capacitor optimization using architectural level current signature prediction

Switching generated supply grid noise presents a potential obstacle to the reduction of supply voltage and resulting power. This paper presents a novel design technique for sizing and placing on-chip decoupling capacitors based on current signatures from the microarchitecture. Simulation of a typical processor workload (SPEC95) provides a realistic stimulation of microarchitecture elements that is coupled with a spatial power grid model. Evaluation of this technique on a typical microprocessor implementation (Alpha 21264) indicates this technique can produce up to a 15% improvement in maximum noise levels over a uniform decoupling capacitor placement strategy.

A hierarchical block-based modeling methodology for SoC in GENESYS

System-on-a-chip (SoC) designs promise to play a dominant role in the future of gigascale integrated (GSI) systems. Existing chip modeling tools based on technology parameters for projecting physical performance are ill suited for projecting the performance of SoC designs. A new modeling methodology for heterogeneous SoCs has been developed for a technology based simulation tool (GENESYS). The hierarchical block modeling methodology mimics the structure of a SoC design by partitioning the chip into blocks as is typical of megacell based design methodologies. The new model allows for exploration of the impact of technology choices on SoC performance for a wide variety of designs. An example SoC is simulated showing improved accuracy of the heterogeneous compared to the homogeneous model. A percentage error of 18.6% for the die size calculation in the homogeneous model is reduced to 3% with the heterogeneous modeling. In addition, the scaling characteristics of the example SoC are shown for the ITRS technology generations. Results show that the same design implemented in 35 nm technology could achieve a factor of 6 increase in clock frequency while operating at less than 1 W on a 5 mm/sup 2/ die.

Modeling technology impact on cluster microprocessor performance

The growing speed gap between transistors and wire interconnects is forcing the development of distributed, or clustered, architectures. These designs partition the chip into small regions with fast intracluster communication. Longer latency is required to communicate between clusters. The hardware and/or software are responsible for scheduling instructions to clusters such that critical path communication occurs within a cluster. This paper presents GENEric SYstems Simulator (GENESYS), a technology modeling tool that captures a broad range of materials, device, circuit, and interconnect parameters across current and future semiconductor technology. This tool is used to explore the relationship between key technology parameters (intercluster wire delay and transistor switching delay) and key architecture parameters (superscalar versus multithreaded instruction dispatch, and value prediction support). GENESYS is used to predict intercluster latencies as VLSI technology advances. The study provides quantitative data showing how conventional superscalar performance is degraded with increasing wire latency. Threaded designs are more tolerant to wire delay. Optimal thread size changes with advancing VLSI technology, suggesting a highly adaptive architecture. Value prediction is shown to be useful in all cases, but provides more benefit to the multithreaded design.

Minimum repeater count, size, and energy dissipation for gigascale integration (GSI) interconnects

Optimal repeater insertion in long interconnects is used to minimize the interconnect response time by mitigating the effects of resistance. The use of this scheme in future high clock frequency designs can lead to an alarming number of required repeaters as predicted by a compact expression for the total number of repeaters. Novel design equations, which significantly decrease the number and power dissipation of these drivers, are derived that minimize the repeater number, size, energy dissipation, or energy-delay product.

Systolic processing architectures using optoelectronic interconnects

Systolic arrays have traditionally provided efficient, high performance execution for computation intensive applications. Despite the extensive research in systolic arrays, system designers must continually incorporate new technological advances to improve node communications, I/O bandwidth, and programmability. This paper presents optoelectronic interconnect as a communication method for systolic arrays in early image processing applications. Optoelectronic interconnects provide potentially high I/O bandwidth required to maintain high utilization rate for systolic arrays. In addition, optoelectronic interconnects provides a two-dimensional focal-plane topology ideal for systolic image processing systems. This paper introduces two new systolic architectures that incorporate integrated optoelectronics to provide an extremely compact, high performance, highly efficient image processing system. Several important early image processing applications developed for these architectures are also described.