Walter Contrata

Double-doped In/sub 0.35/Al/sub 0.65/As/In/sub 0.35/Ga/sub 0.65/As power heterojunction FET on GaAs substrate with 1 W output power

A double-doped metamorphic In/sub 0.35/Al/sub 0.65/As/In/sub 0.35/Ga/sub 0.65/As power heterojunction FET (HJFET) on GaAs substrate is demonstrated. The HJFET exhibits good dc characteristics, with gate forward turn on voltage of 1.0 V, breakdown voltage of 20 V, and maximum drain current of 490 mA/mm. Under RF operation at a frequency of 950 MHz, a power added efficiency of 63% with associated output power of 31.7 dBm is obtained at a gate width of 12.8 mm. This large gate width and state-of-the-art power performance in metamorphic HJFETS were enabled by a selective etching, sputtered WSi gate process and low surface roughness due to an Al/sub 0.60/Ga/sub 0.40/As/sub 0.69/Sb/sub 0.31/ strain relief buffer.

Gate length scaling for Al/sub 0.2/Ga/sub 0.8/N/GaN HJFETs: two-dimensional full band Monte Carlo simulation including polarization effect

Two-dimensional self-consistent full band Monte Carlo (FBMC) simulator was developed for electron transport in wurtzite phase AlGaN/GaN heterojunction (HJ) FET. Recessed gate Al/sub 0.2/Ga/sub 0.8/N/GaN HJFET structures with an undoped cap layer were simulated, where the spontaneous and piezoelectric polarization effects were taken into account. The polarization effect was shown to not only increase the current density, but also improve the carrier confinement, and hence improve the transconductance. An off-state drain breakdown voltage (BV/sub ds/) of 300 V and a maximum linear output power (P/sub max/) of 46 W/mm were predicted for a 0.9-/spl mu/m gate device. For a 0.1-/spl mu/m gate device, 60 V BV/sub ds/, 20 W/mm P/sub max/, and 160 GHz current-gain cutoff frequency were predicted. Although there is considerable uncertainty due to lack of information on the band structure, scattering rates, and surface conditions, the present results indicate a wide margin for improvements over current performance of AlGaN/GaN HJFETs in the future. To our knowledge, this is the first report on the FBMC simulation for AlGaN/GaN HJFETs.

Intermodulation distortion simulation using physical GaAs FET model

Intermodulation distortion is simulated using a physical GaAs FET model for the first time, to our knowledge. A GaAs FET power amplifier, including input and output circuits, is examined. For the FET, a fully 2-dimensional Monte Carlo simulator is used. The simulated P/sub IN/-P/sub OUT/ performance is in fair agreement with measured data. Gain and phase compression (AM-PM) characteristics are simulated, and correlated to features in the RF I-V characteristics. Finally, third order intermodulation distortion is estimated from the AM-PM characteristics and compared to measurement, with qualitative agreement. This technique advances the art of computer aided design of nonlinear devices because it allows the prediction of distortion characteristics before undertaking an expensive and time-consuming device fabrication.

Monte Carlo simulation for electron transport in MESFETs including realistic band structure of GaAs

A full band Monte Carlo (FBMC) simulator was developed for electron transport in GaAs MESFETs. As a result of increased scattering rate due to the complicated band structure, the average velocity in the high field region was lower than the analytical band Monte Carlo (ABMC) result. Also, the simulated energy peak was higher than the ABMC result, due to electrons populating the upper bands. Not only due to a limited number of the first conduction band states capable of ionization, but also due to a small mass of the second conduction band, more than 95% of ionization events were shown to occur in the upper bands. The simulated ionization rate lies within the range of experimental results. To our knowledge, this is the first report on the full band two-dimensional (2-D) self-consistent GaAs MESFET simulation.

Microwave noise properties for resonant tunneling transistors (RTTs)

We propose and demonstrate a low noise amplifier utilizing the negative input conductance of resonant-tunneling transistors (RTTs). The fabricated RTTs, which integrate a resonant-tunneling diode (RTD) into the source of a heterojunction FET (HJFET), exhibited a negative input conductance at low frequencies (/spl les/10 GHz). When the gate bias is close to the resonance peak not only F/sub min/ but also R/sub n/ increases at low frequencies. Also, F/sub min/ shows a sharp dip at the valley current these behaviors are explained by shot noise generation at the RTD. Theoretical results suggest that reducing the valley current as well as reducing the series resistance would realize RTT noise performance superior to HJFETs.

Full band Monte Carlo simulation for temperature-dependent electron transport in gallium nitride

Abstract A fast and compact full band Monte Carlo electron transport simulator has been developed, which can run on a personal computer. High-temperature transport simulation was demonstrated for GaN, and it predicts small temperature dependence of peak velocity and reduction of impact ionization at high temperature.

InAs/GaAs graded superlattice channel transistors (GSTs)

Pseudomorphic high electron mobility transistors (PHEMTs) offer superior power and noise performances compared to conventional HEMTs. However, as gate voltage increases, PHEMTs still suffer from parallel conduction of electrons in doped AlGaAs. This effect not only decreases transconductance (g/sub m/) at high gate bias but also degrades power gain and efficiency for large-signal operation. High indium content channel would allow an increase in conduction band offset, and hence, suppression of the parallel conduction, but due to the lattice mismatch, the reliability of the device might be affected, and therefore, the maximum allowable InAs mole fraction is limited. In this paper, we propose a graded superlattice channel transistor (GST), which reduces parallel conduction while suppressing an increase of strain in the channel.