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Dive into the research topics where Kazuaki Kunihiro is active.

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Featured researches published by Kazuaki Kunihiro.


IEEE Electron Device Letters | 1999

Experimental evaluation of impact ionization coefficients in GaN

Kazuaki Kunihiro; K. Kasahara; Yuji Takahashi; Yasuo Ohno

The impact ionization coefficient of electrons (/spl alpha//sub n/) in GaN is determined as a function of the electric field strength from gate-current analysis in the prebreakdown regime of AlGaN/GaN heterojunction field effect transistors (HJFETs). The experimentally obtained /spl alpha//sub n/, where the assumed effective length of the high electric field is precisely defined since its upper bound is closely limited due to the small gate-drain separation, agrees with that extrapolated from Monte Carlo simulation. It is experimentally confirmed that the breakdown field of GaN is higher than that of GaAs by a factor of about eight.


IEEE Transactions on Electron Devices | 1996

A large-signal equivalent circuit model for substrate-induced drain-lag phenomena in HJFETs

Kazuaki Kunihiro; Yasuo Ohno

A large-signal HJFET model is developed for drain-lag phenomena caused by deep traps beneath the channel. The model is based on the self-backgating and Shockley-Read-Hall (SRH) statistics. It is shown by two-dimensional (2D) device simulation that electron capture in deep traps is much faster than electron emission under large-signal conditions; therefore, drain current exhibits different responses for rising and falling steps of applied voltage. In the circuit model, electron capture and emission in deep traps are expressed by a parallel circuit consisting of a diode and a resistor, which are physically deduced from SRH statistics. The model agrees well with the 2D simulation results and experimental current-transient data for large-signal voltage steps. In addition, this model accurately describes small-signal drain-conductance dispersion and temperature effects on the trapping phenomena.


IEEE Journal of Solid-state Circuits | 2012

A 30-MHz–2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems

Masaki Kitsunezuka; Hiroshi Kodama; Naoki Oshima; Kazuaki Kunihiro; Tadashi Maeda; Muneo Fukaishi

A 30-MHz-2.4-GHz complementary metal oxide semiconductor (CMOS) receiver with an integrated tunable RF filter and a dynamic-range-scalable energy detector for both white-space and interference-level sensing in cognitive radio systems is reported. The second-order RF filter has only two stacked transistors, and its use, in combination with a subsequent harmonic rejection mixer, results in wideband interference rejection. The energy detector with programmable rectifiers provides dynamic-range (DR) scalability, enabling shared use for white-space/interference-level detection and automatic gain control. A prototype chip, fabricated using 90-nm CMOS technology, achieved over 42-dB harmonic rejection including 7th-order component without any external device, a 67-dB gain, a 5-8-dB noise figure, a -11-dBm in-band third-order intercept point, and a +38-dBm second-order intercept point while drawing only 25-37 mA from a 1.2-V power supply. Multi-resolution DR-scalable spectrum sensing with a 0.2-30-MHz detection bandwidth, -83-dBm minimum sensitivity, and a 29-48-dB DR was demonstrated.


radio frequency integrated circuits symposium | 2004

A diplexer-matching dual-band power amplifier LTCC module for IEEE 802.11a/b/g wireless LANs

Kazuaki Kunihiro; Shingo Yamanouchi; Takashi Miyazaki; Yuuichi Aoki; K. Ikuina; T. Ohtsuka; Hikaru Hida

We have developed a compact dual-band (2.4/5 GHz) power-amplifier module with a concurrent two-stage InGaP/GaAs HBT for triple-mode (IEEE 802.11a/b/g) WLANs. The proposed diplexer-matching network is three-dimensionally implemented in an LTCC substrate (5/spl times/5 mm). The module exhibits an output power of 20 dBm at 2.4 GHz, and 18 dBm at 5.25 GHz with an error vector magnitude of 4-5% for a 54-Mbps OFDM signal. Our approach of using a concurrent dual-band PA reduces the size and cost by almost half compared with using a conventional parallel PA.


IEEE Transactions on Electron Devices | 1993

Numerical analysis of kink effect in HJFET with a heterobuffer layer

Kazuaki Kunihiro; Hitoshi Yano; Norio Goto; Yasuo Ohno

The kink effect in an AlGaAs/GaAs HJFET with a heterobuffer layer is investigated using a two-dimensional device simulator with impact ionization and deep-trap models. It is confirmed that the accumulation of holes generated by impact ionization causes the kink effect. The influence of deep levels on the kink characteristics is also investigated. The kink effect is suppressed by electron traps in the channel region through the recombination of the generated holes. On the other hand, the kink effect is enhanced by hole traps, which are positively ionized by increases in hole concentration. However, excessive hole trap concentration suppresses the accumulation of holes, due to enhanced recombination with electrons. Under such conditions the kink effect vanishes. >


custom integrated circuits conference | 2004

An efficient algorithm for simulating error vector magnitude in nonlinear OFDM amplifiers

Shingo Yamanouchi; Kazuaki Kunihiro; Hikaru Hida

We have developed an algorithm for evaluating the error vector magnitude (EVM) from the single-tone distortion of power amplifiers in orthogonal frequency-division multiplexing (OFDM) systems. The developed formulas allow us to simulate EVM using only the single-tone response i.e. without modulation and demodulation; this enables us to easily calculate the EVM using a standard harmonic-balance (HB) simulator. This simulation scheme reduces the processing time by a factor of ten compared with conventional system-level (SL) simulation. The EVM obtained using this scheme agreed well with the results of SL simulation (0.6% error).


radio frequency integrated circuits symposium | 2008

An envelope tracking power amplifier using an adaptive biased envelope amplifier for WCDMA handsets

Kiyohiko Takahashi; Shingo Yamanouchi; Tomohisa Hirayama; Kazuaki Kunihiro

An envelope tracking power amplifier (ET-PA) using a self-oscillation pulse-width-modulation circuit with an adaptive bias technique is presented. In this technique, the supply voltage to the envelope amplifier is changed depending on the output power level. Since this approach enables the envelope amplifier to change the output power without degrading the signal resolution, the developed ET-PA shows a low adjacent channel leakage power ratio (ACPR) of less than -38 dBc in a wide output power range from 10 to 27 dBm. The ET-PA shows 45.4% overall efficiency at peak output power of 28 dBm. The average efficiency was 29%, which is 2.4 times higher than that of a class-AB PA. The noise power in the receive band (Rx noise) is -136 dBm/Hz at output power of 26 dBm at a frequency of 2.14 GHz.


radio frequency integrated circuits symposium | 2011

A 0.7-3GHz envelope ΔΣ modulator using phase modulated carrier clock for multi-mode/band switching amplifiers

Shinichi Hori; Kazuaki Kunihiro; Kiyohiko Takahashi; Muneo Fukaishi

A 1-bit RF modulator using phase-modulated-carrier-clocking envelope ΔΣ modulation for a multi-mode/band transmitter is presented. The prototype IC designed in 90 nm CMOS process covers 2.4 GHz ISM and 3GPP frequency bands up to 3 GHz in conformity with IEEE 802.11g, W-CDMA and LTE in 5MHz-mode. The IC dissipates 8 mW for 1.95 GHz WCDMA and occupies 0.044 mm2.


IEEE Transactions on Microwave Theory and Techniques | 2007

Analysis and Design of a Dynamic Predistorter for WCDMA Handset Power Amplifiers

Shingo Yamanouchi; Yuuichi Aoki; Kazuaki Kunihiro; Tomohisa Hirayama; Takashi Miyazaki; Hikaru Hida

This paper presents a dynamic predistorter (PD), which linearizes the dynamic AM-AM and AM-PM of a wideband code division multiple access handset power amplifier (PA). The dynamic PD allows an adjacent channel leakage power ratio (ACPR) improvement of 15.7 dB, which is superior to conventional PDs that linearize static AM-AM and AM-PM. The dynamic PD was designed using an HBT generating nonlinearity, a short circuit at the baseband (les4 MHz), and a load circuit for the HBT at the RF fundamental band (ap1.95 GHz). Volterra-series analysis was performed to understand the mechanism of the dynamic PD. The analysis revealed that the short circuit at the baseband enabled the dynamic PD generating third-order intermodulation distortion (IMD3) with opposite phase to the fundamental tone (i.e., antiphase IMD3). The antiphase IMD3 allows dynamic gain compression, which linearizes the dynamic gain expansion of a PA with low quiescent current. The analysis also revealed that the IMD3 amplitude of the dynamic PD can be adjusted by load impedance at the RF fundamental band, which enables the gradient of dynamic AM-AM and AM-PM to be optimized to linearize the PA. The fabricated two-stage InGaP/GaAs HBT PA module with the dynamic PD exhibited an ACPR of -40 dBc and a power-added efficiency of 50% at an average output power of 26.8 dBm with a quiescent current of 20 mA


IEEE Transactions on Electron Devices | 2000

Gate length scaling for Al/sub 0.2/Ga/sub 0.8/N/GaN HJFETs: two-dimensional full band Monte Carlo simulation including polarization effect

Yuji Ando; Walter Contrata; Norihiko Samoto; Hironobu Miyamoto; Kohji Matsunaga; Masaaki Kuzuhara; Kazuaki Kunihiro; K. Kasahara; Tatsuo Nakayama; Yuji Takahashi; Nobuyuki Hayama; Yasuo Ohno

Two-dimensional self-consistent full band Monte Carlo (FBMC) simulator was developed for electron transport in wurtzite phase AlGaN/GaN heterojunction (HJ) FET. Recessed gate Al/sub 0.2/Ga/sub 0.8/N/GaN HJFET structures with an undoped cap layer were simulated, where the spontaneous and piezoelectric polarization effects were taken into account. The polarization effect was shown to not only increase the current density, but also improve the carrier confinement, and hence improve the transconductance. An off-state drain breakdown voltage (BV/sub ds/) of 300 V and a maximum linear output power (P/sub max/) of 46 W/mm were predicted for a 0.9-/spl mu/m gate device. For a 0.1-/spl mu/m gate device, 60 V BV/sub ds/, 20 W/mm P/sub max/, and 160 GHz current-gain cutoff frequency were predicted. Although there is considerable uncertainty due to lack of information on the band structure, scattering rates, and surface conditions, the present results indicate a wide margin for improvements over current performance of AlGaN/GaN HJFETs in the future. To our knowledge, this is the first report on the FBMC simulation for AlGaN/GaN HJFETs.

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