Kyuho Cho

Low leakage ZrO2 based capacitors for sub 20 nm dynamic random access memory technology nodes

During dynamic random access memory (DRAM) capacitor scaling, a lot of effort was put searching for new material stacks to overcome the scaling limitations of the current material stack, such as leakage and sufficient capacitance. In this study, very promising results for a SrTiO3 based capacitor with a record low capacitance equivalent thickness value of 0.2 nm at target leakage current are presented. Due to the material properties of SrTiO3 films (high vacancy concentration and low band gap), which are leading to an increased leakage current, a physical thickness of at least 8 nm is required at target leakage specifications. However, this physical thickness would not fit into an 18 nm DRAM structure. Therefore, two different new approaches to develop a new ZrO2 based DRAM capacitor stack by changing the inter-layer material from Al2O3 to SrO and the exchange of the top electrode material from TiN to Pt are presented. A combination of these two approaches leads to a capacitance equivalent thickness value...

Ultra-thin ZrO2/SrO/ZrO2 insulating stacks for future dynamic random access memory capacitor applications

Aiming for improvement of the ZrO2-based insulator properties as compared to the state-of-the-art ZrO2/Al2O3/ZrO2 stacks beyond 20 nm dynamic random access memory (DRAM) technology applications, ultra-thin (5 nm) ZrO2/SrO/ZrO2 stacks with TiN electrodes deposited by physical vapor deposition are addressed. By replacing the Al2O3 interlayer with SrO, the effective dielectric permittivity of the stack can be increased as indicated by electrical analysis. At the same time, no degradation of the insulating properties of the SrO-containing stacks and minor changes in the reliability, compared to an Al2O3 interlayer, are found. These results are indicating the possibility of further reducing the effective oxide thickness of the ZrO2-based stacks to come close to 0.5 nm for future DRAM capacitors.

A robust alternative for the DRAM capacitor of 50 nm generation

As a new alternative for the DRAM capacitor of 50 nm generation, Ru/Insulator/TiN (RIT) capacitor with the lowest Toxeq of 0.85 nm has been successfully developed for the first time. TiO/sub 2//HfO/sub 2/ and Ta/sub 2/O/sub 5//HfO/sub 2/ double-layers were used as dielectric materials. After full integration into 512 Mbits DRAM device, the RIT capacitor showed good electrical properties and thermal stability up to 550/spl deg/C and its time-dependent-dielectric-breakdown behavior sufficiently satisfied 10-year lifetime within a DRAM operation voltage.

Origin of Leakage Paths Driven by Electric Fields in Al‐Doped TiO2 Films

The growth of leakage current paths in Al-doped TiO2 (ATO) films is observed by in situ TEM under negative bias stress. Through systematic HAADF-STEM, STEM-EDS, and STEM-EELS studies, it is confirmed that the electric field-induced growth of the Ru-doped TiO2 phase is the main reason for the ATO films negative leakage.

Interface Analysis of MIM Capacitor Using ZrN Electrodes and ALD-ZrO2 Dielectrics

Due to the downscaling of the devices like DRAM capacitor, introduction of new metal electrodes and high-k materials is indispensable for meeting the future device performance. A wide variety of DRAM capacitor electrodes are currently being evaluated as replacements for TiN including ZrN, HfN, and Ru. Rubase electrode has advantage of high work function but also has cost and integration problem. Thermally robust HfN/HfO2 gate stack structure was reported with scaling down of equivalent oxide thickness (Toxeq.) less than 10 and several attempts to prepare HfN films with organometallic Hf precursors by metal organic chemical vapor deposition (MOCVD) have been continued [1,2]. Even though Zirconium nitride exhibits high melting point, chemical inertness, and about 0.5eV-higher work function than TiN, very little is known about its qualities as capacitor electrode [3]. On the other hand, ZrO2 film has been spotlighted as new dielectric material in TiN/Insulator/TiN (TIT) capacitor replacing HfO2 film, due to its high dielectric constant, wide band gap, and thermal stability [4]. In this study, we fabricated new MIM capacitor using ZrN electrode and ALD ZrO2 dielectric for DRAM capacitor. ZrN films (100~1000 ) were deposited at different temperatures ranging from 25 to 500 by reactive magnetron sputtering. ZrO2 films were used as a dielectric by atomic layer deposition (ALD) method with Tetra-Ethyl-Methyl-Amino-Zirconium (TEMAZ) liquid precursor and O3 reactant at the temperature of 250 . Electrical properties of MIM capacitor with ZrN/ZrO2 combination such as capacitance, leakage current density and dielectric constant were compared with TiN/ZrO2 stack. Composition, interfacial reaction, and crystalline structure of ZrN and ZrO2 films were analyzed by Rutherford backscattering spectroscopy (RBS), X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), and transmission electron microscopy (TEM). Furthermore, the specific resistivites and the work functions of the films were evaluated and the results will be discussed in detail.

Evaluation of Novel Sr Precursors for Atomic Layer Deposition of SrO Thin Film

Atomic layer deposition (ALD) process to deposit SrO film using novel Sr precursor – Sr (Methoxy-TetramethylHeptadiene)2 was estimated. Fig.1 showed the chemical structure of the synthesized Sr(MTHD)2. Fig. 2 showed thermal gravimetric analysis results of Sr(MTHD)2 and commercially used Sr (Tetra-Methyl Hetadiene)2. 50 % precursor evaporation temperature (T50) of Sr (MTHD)2 was 330 C, which was 30 C lower than that of Sr(TMHD)2. Liquid delivery system with flash evaporator was used to transport the precursors to substrate. The precursors were dissolved in Tetra Hydro Furan (THF) to prevent clogging during the delivery process. Ozone was used as a reactant to deposit SrO. It was found that thickness uniformity range of SrO film on Si wafer was less than 2 %. The deposition rate of SrO film using new Sr precursor was 0.4 A/cycle, which was almost same regardless of substrate temperatures up to 400 C. High vapor pressure and good thermal stability of new Sr precursor make it promising candidates for ALD precursors to deposit SrTiO3, aSrTiO3. Fig.1. Chemical structure of Sr(MTHD)2

Schottky barrier height engineering for next generation DRAM capacitors

DRAM capacitors are reaching the scaling limit and new approaches are necessary to enable further reduction of the physical thickness of the capacitor dielectric. The Schottky Barrier Height (SBH) of a noble metal electrode (Pt) on atomic layer deposited ZrO2/Al2O3/ZrO2 (ZAZ, 6 nm) was evaluated and compared to a TiN electrode. Internal Photo Emission Spectroscopy (IPE) and Photoconductivity measurement (PC) were used to estimate the SBH and band gap, respectively. The SBH difference between the two electrodes was evaluated in comparison with a previously reported model. Finally, the impact of an increased SBH on dielectric scaling will be discussed based on a leakage current simulation of a ZrO2 capacitor.

Evaluation of ALD grown strontium-doped HfO 2 thin films as capacitor dielectric for 40nm DRAM Device and beyond

Introduction As the innovative scale-down of DRAM device continues, 40nm generation becomes close at hand. To satisfy the cell capacitance of 25fF in 40nm design rule, the equivalent oxide thickness (EOT) of a dielectric material should be as low as 0.5nm. TiN/insulator/TiN(TIT) capacitor using HfO2 has been successfully developed for 70nm generation.[1] Therefore the scale-down of DRAM device has required new high-k dielectric and electrode. When high-k dielectrics, such as Ta2O5 or TiO2 , were implemented as the dielectric of the TIT capacitor, it was difficult to suppress the leakage current because of low Schottky barrier height and poor interface due to interaction between TiN and the dielectrics. (Figure 1). On the other hand, Ru/Insulator/Ru (RIR) capacitor using high-k dielectrics has an advantage of EOT scaling down, but also has some problems yet to be solved, such as the contact-plug oxidation and Ru electrode agglomeration during the back-end process. Because tetragonal phase of HfO2 is stable at high temperature, it is important to reduce the crystallization temperature to tetragonal phase. In this study, we attempted to make tetragonal HfO2 films by atomic layer deposition using strontium doping for dielectric material of TIT capacitor. HfO2 predominantly crystallizes in the lower k monoclinic phase, instead of forming the high k tetragonal phase in pure form.[2] Therefore, it has been reported that formation of tetragonal HfO2 films by other material doping [3], and stabilizers with relatively low temperature has importance in essence. We have introduced Sr doped HfO2 thin films for high-k dielectric layers. We have investigated the crystallization behavior of Sr doped HfO2 films and electrical characteristics of TITSr doped HfO2 (Sr-HfO2 ) capacitors.

Ru/TiO2/ZrO2/TiN (RIT-TiO2/ZrO2) Capacitor Structure for the 50nm DRAM Device and beyond

Advanced Process Development Team, *Process Development Team, Semiconductor R&D Division, Samsung Electronics Co., Ltd. San#24 Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do, Korea 449-711 E-mail: soon310.lim@samsung.com Introduction As the innovative scale-down of DRAM device continues, 50nm generation becomes close at hand. As shown in Fig. 1, to satisfy the cell capacitance of 25fF with 1.7μm storage-node height in 50nm design rule, the equivalent oxide thickness (Toxeq.) of a dielectric material should be as low as 0.8nm. TiN/HfO2/TiN (TIT) capacitor has been successfully developed for 70nm generation [1], but it seems to be difficult to meet the requirements for sub-60nm device. When Ta2O5 or TiO2 was implemented as the dielectric of the TIT capacitor to reduce Toxeq. below 1.2nm, it was difficult to suppress the leakage current because of low barrier height and poor interface between TiN and high-k dielectric (Figure 2). On the other hand, Ru/Insulator/Ru (RIR) capacitor using high-k dielectrics has some problems yet to be solved, such as the contact-plug oxidation and Ru electrode agglomeration during the back-end process. In the previous study [2], we have proposed Ru(top)/Insulator/TiN(bottom) capacitor as an alternative for the DRAM capacitor below 50nm generation. The leakage currents of Ta2O5 and TiO2 could be reduced by the application of Ru top electrode. And also a reliable storage-node was obtained with solid TiN bottom electrode. RIT-Ta2O5/HfO2 was successfully developed corresponding to Toxeq. 1.1nm with 1fA/cell leakage current after full integration. In this study, to reduce Toxeq. value lower than 0.8nm, we have introduced ZrO2 as dielectric layers. We have compared and discussed the electrical characteristics of RIT-TiO2/ZrO2 and RIT-TiO2/HfO2 capacitors. The electrical properties after back-end metal-line integration and time-dependent-dielectricbreakdown behavior were also investigated .