Wanda Gass

A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array

A 64-tap FIR (finite-impulse-response) digital filter fabricated in a 0.8- mu m, triple-level interconnect, BiCMOS gate-array technology is discussed. The filter has been tested and is fully functional at 100-MHz sampling rate. These results are obtained by combining an optimized architecture and gate-array floor planning with submicron BiCMOS technology. A total design time of one week was achieved using a filter compiler. About two-thirds (49 mm/sup 2/) of the 100 K gate-array core was allocated to the filter. The design is equivalent to about 55 K gates (two-input NAND gates) in complexity and utilizes 76% of the core allocation. The device input/output are 100 K emitter-coupled logic (ECL) compatible. The functional switching waveforms of the master clock, least-significant-bit (LSB) input, and most-significant-bit (MSB) output at 1.00-MHz operating frequency are shown.<<ETX>>

Microcomputer device having test mode substituting external RAM for internal RAM

A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expansion mode, with the opcode returned by an external data bus, or all program storage can be off-chip in a system emulator mode. The ALU and accumulator have 32-bit data paths, while the busses are 16-bit. Various test modes are permitted; for example, the internal program ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes. Alternatively, the internal data RAM may be disabled and an external RAM used, for which a three-state or four-state instruction execution sequence is established instead of one per state to allow an operand to be transferred in on the data bus and high and low words of the accumulator transferred out; this node is very useful for checking ALU operations not otherwise accessible off-chip.

A functional silicon compiler for high speed FIR digital filters

A functional compiler system for the implementation of high-speed finite impulse-response (FIR) digital filters on gate-array ICs is presented. The system is capable of implementing complex digital filters directly from frequency-domain specifications. Fast turnaround and sample rates in excess of 100 MHz are achieved by using a combination of architectural optimization and advanced 0.8- mu m BiCMOS gate-array technology. A 64-tap FIR digital filter synthesized using this new functional compiler system is presented. It has been fabricated and tested fully functional at a sample frequency of 100 MHz.<<ETX>>

Implementation options for WCDMA

This paper discusses the design tradeoffs and implementation options for building wideband CDMA systems. System on a chip (SOC) solutions have a range of implementation options, from processor cores to custom ASIC (or a mix of both), to satisfy the extremely challenging requirements of the digital baseband of a next generation wireless system. Additionally, good designs should have a roadmap that will take advantage of rapid improvements in process technology. This paper describes the use of coprocessors alongside DSPs to meet the demanding computational requirements of WCDMA. We show that a coprocessor based design still achieves reasonably efficient area and power use, maintains a high degree of programmability and has a good technology migration path.

Architecture trends of MPEG decoders for set-top box

Since its introduction as a consumer product in 1994, the digital set-top box has experienced rapid growth and is predicted to grow at an even stronger rate through the end of this decade. In just the past three years, the architecture of the MPEG decoders have experienced several changes. Initially the audio and video decoder were separate chips, but recently they have been integrated onto a single chip along with the transport, encryption, and user interface functions of the set-top box. In addition to a higher level of integration, the system memory requirements have been reduced and more features for the end user have been added. In the future, the remainder of the digital functions in the set-top box will be integrated onto a single chip. To be successful in providing a cost effect solution, a mixture of hardware and software modules will be needed to provide the appropriate amount of flexibility and the smallest implementation. The hardware/software partitioning will change with each technology node until a fully programmable implementation becomes the most cost effective solution.

Hi-PASS: a computer-aided synthesis system for maximally parallel digital signal processing ASICs

Hi-PASS, a CAD system for digital signal processor (DSP) architecture synthesis, has been developed to automatically produce maximally parallel VLSI designs for real-time applications. The target DSP applications are the class for which desired sample rates are so high that time sharing of hardware is not feasible. Hi-PASS accepts a C code description of the design to be synthesized and produces a structural description of the final design which can be fabricated using standard cells provided by the Lager IV silicon assembly system. Hi-PASS is a collection of modular tools, several of which contain new techniques within the field of synthesis. C code is converted into a flowgraph using a technique known as symbolic interpretation, including new methods for handling certain types of input-dependent control flow. The HOPS program is a heuristic search flowgraph optimizer tailored for the arithmetic intensive structures necessary for real-time DSP applications. The high throughput rates necessary for these applications also require that retiming be used to provide very short inter-register delay times. A new retiming tool has been developed which allows for computationally efficient bit-level retiming.<<ETX>>

Advances in hardware design and implementation of signal processing systems [DSP Forum]

This IEEE Signal Processing Magazine (SPM) forum discusses advances, challenges, and future trends in hardware design and implementation of signal processing (SP) systems. The invited forum members who bring their expert insights are: Prof. Shuvra S. Bhattacharyya (University of Maryland, College Park), Jeff Bier [Berkeley Design Technology, Inc. (BDTI)], Dr. Wanda K. Gass (Texas Instruments), Dr. Ram K. Krishnamurthy (Intel), and Prof. Edward A. Lee (Univerisity of California, Berkeley and BDTI). The moderator of the forum is Dr. Konstantinos Konstantinides (Hewlett-Packard and associate editor of SPM). Our readers may agree or disagree with the ideas discussed next. In either case, we invite you to share your comments with us by e-mailing to SPM_columns_forums@yahoo.com.

Vision model based video perceptual distortion measure for video processing and applications

A perceptual video distortion measure system based on the human vision model is presented. This system is an extension of the still perceptual distortion measure system. One advantage of the distortion measure is that the distortion can be weighted for frames in the vicinity of scene cuts. Our video distortion measure also requires less computation compared to other approaches. The perceptual distortion measure has wide use in video processing and applications, such as in the selection of the quantization matrices, the selection of the mquant parameter, and as a criterion for mode decision in MPEG encoders. Simulation results are presented.

Video perceptual distortion measure: two-dimensional versus three-dimensional approaches

In this paper the two-dimensional and three-dimensional video perceptual distortion measure systems based on the human vision model are presented. These systems are extensions of the still perceptual distortion measure system. One advantage of the two-dimensional video distortion measure is that the distortion can be weighted for frames in the vicinity of scene cuts. The two-dimensional video distortion measure also requires less computation compared to the three-dimensional video distortion measure. Simulation results are presented.

A parallel signal processor system

As digital signal processor (DSP) devices become more prevalent, a need has developed to support not only dedicated, single device applications, but also to provide system architectures which support multiple DSP requirements. Multiple, or parallel. DSP systems can quickly leverage the power of single devices into powerful processors capable of solving the most complex signal processing problems. This paper describes a specific implementation of a multiple DSP system which is being used to solve a problem in speech recognition.