Surendar S. Magar

A microcomputer with digital signal processing capability

A single microcomputer for realtime digital signal processing and high-speed controller applications, with a 200ns instruction cycle, 16 × 16 parallel multiplier, 32b arithmetic unit, 144 by 16 data memory, a 1536 by 16 program and coefficient memory, will be discussed.

Microcomputer device having test mode substituting external RAM for internal RAM

A digital data processing system employs a single-chip microcomputer device having separate on-chip program and data memory, executing instructions in a single machine state. An external program address bus allows off-chip program fetch in a memory expansion mode, with the opcode returned by an external data bus, or all program storage can be off-chip in a system emulator mode. The ALU and accumulator have 32-bit data paths, while the busses are 16-bit. Various test modes are permitted; for example, the internal program ROM may be read out on the data bus, one opcode at a time, for test purposes without executing the opcodes. Alternatively, the internal data RAM may be disabled and an external RAM used, for which a three-state or four-state instruction execution sequence is established instead of one per state to allow an operand to be transferred in on the data bus and high and low words of the accumulator transferred out; this node is very useful for checking ALU operations not otherwise accessible off-chip.

An NMOS digital signal processor with multiprocessing capability

This paper will describe a second generation 8-13MIP multi-tasking DSP with a 544×16b RAM and single cycle multiply/accumulation instructions. The chip is implemented with 2.4μ NMOS technology.

A second-generation digital signal processor

The architecture, implementation, and applications of the TMS32020, a second-generation VLSI digital signal processor, are described. The processor has many special features which provide a significant advance over previous VLSI digital signal processors. Its multiprocessor capabilities further distinguish it, allowing for much more flexibility in overall system design. The architecture of the device allows a dual bus structure to be maintained on-chip, while external bus hardware requirements are minimized via the multiplexing of these buses externally. Some of the notable features incorporated onto the device include two large on-chip RAM blocks, large external program/data address spaces, single-cycle multiply/accumulate instructions, hardware and instructions for efficient memory management, and a versatile multiprocessor interface.

Architecture for DSP VLSI

AS CMOS technology scales to 1μm, it is becoming possible to integrate more than 500K transistors on a processor-like chip. At this point, various digital signal processing (DSP) chip architecture approaches need to be re-examined to enable VLSI designers to obtain on optimal solution for system designers in terms of performance, power, cost, flexibility and development time. The panel will explore and debate several DSP architectural options available to VLSI designers, such as single-processor, systolic arrays, parallel processors, customs, etc.