Ashwin H. Shah

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

A trench transistor cross-point DRAM cell

A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.

A 4Mb DRAM with cross point trench transistor cell

This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.

High-performance BiCMOS 100 K-gate array

A BiCMOS gate array in 0.8- mu m technology with CMOS intrinsic gate delays of 100 ps plus 60 ps/fan-out and BiCMOS intrinsic delays of 200 ps with a 17-ps/fan-out drive factor is discussed. A compact base cell (750 mu m/sup 2//gate) has been designed with full bipolar drive capability for the efficient layout of both primitive gates and large-arrayed macros, such as register files and multipliers. A 106 K-gate array has been built on a 1.14-cm/sup 2/ chip with ECL I/O capability. The place and route in three levels of metal provide array utilization greater than 90%. The gate array was used to implement a 74 K-gate filter design with testability features such as JTAG and two-phase scan. >

A 100 MHz 64-tap FIR digital filter in a 0.8 mu m BiCMOS gate array

A 64-tap FIR (finite-impulse-response) digital filter fabricated in a 0.8- mu m, triple-level interconnect, BiCMOS gate-array technology is discussed. The filter has been tested and is fully functional at 100-MHz sampling rate. These results are obtained by combining an optimized architecture and gate-array floor planning with submicron BiCMOS technology. A total design time of one week was achieved using a filter compiler. About two-thirds (49 mm/sup 2/) of the 100 K gate-array core was allocated to the filter. The design is equivalent to about 55 K gates (two-input NAND gates) in complexity and utilizes 76% of the core allocation. The device input/output are 100 K emitter-coupled logic (ECL) compatible. The functional switching waveforms of the master clock, least-significant-bit (LSB) input, and most-significant-bit (MSB) output at 1.00-MHz operating frequency are shown.<<ETX>>

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8- mu m BiCMOS process, the chip uses 117- mu m/sup 2/, full-CMOS, six-transistor memory cells and measures 6.5*8.15 mm/sup 2/. The design methodology described here illustrates the extent to which bipolar devices can be integrated into the periphery of a CMOS memory array. This integration was achieved through the use of a novel sensing scheme which provided three stages of bipolar differential sensing, with the first stage of sensing taking place directly on the bit lines. >

A functional silicon compiler for high speed FIR digital filters

A functional compiler system for the implementation of high-speed finite impulse-response (FIR) digital filters on gate-array ICs is presented. The system is capable of implementing complex digital filters directly from frequency-domain specifications. Fast turnaround and sample rates in excess of 100 MHz are achieved by using a combination of architectural optimization and advanced 0.8- mu m BiCMOS gate-array technology. A 64-tap FIR digital filter synthesized using this new functional compiler system is presented. It has been fabricated and tested fully functional at a sample frequency of 100 MHz.<<ETX>>

Trench capacitor leakage in Mbit DRAMs

The limitations on trench capacitors imposed by leakage mechanisms in high density DRAMs has been studied through simulations. The primary purpose of the work has been to investigate all possible leakage mechanisms and to determine the optimum substrate doping profile for which the trench capacitor leakage is sufficiently suppressed. The effect of all relevant structural, process and electrical parameters on the required substrate doping profile is also fully investigated. The substrate doping density at which impact ionization causes avalanche breakdown at the trench capacitor junction has also been estimated. It is shown that for trench spacing of 0.75 µm or more. an intermediate range of substrate doping concentrations can always be found for which both the trench leakage and the junction breakdown can be avoided.