Wayne Greene

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

0.18 um dual Vt MOSFET process and energy-delay measurement

A 0.18 um dual Vt MOSFET process has been developed. The low Vt devices are used for logic and the high Vt device for power control. The low Vt NMOS and PMOS have threshold voltages of 80 mV and 100 mV at nominal channel length, and Ion/Ioff of 340/0.05 uA/um and 123/0.03 uA/um respectively under 1V Vdd. The NMOS current drive at 0.6V Vdd has a 40% improvement over the best reported to date. Energy-delay (ED) extracted from measured device data was investigated over Vdd and Vt parameter space for the first time. The results show that: (1) Optimum Vt/Vdd corresponding to minimum energy-delay product for a typical application is around 120/300 mV and leads to modest performance. (2) The optimum Vt is a logarithmic function of the typical activity factor of the application. (3) The dual Vt process is important for applications with high idling factor and brings about a 2.5X improvement in energy-delay product or 50% improvement in speed with the same energy over a single standard Vt process for an application with a 98% idling factor.

Indium transient enhanced diffusion

Indium, an acceptor dopant in silicon, is a large atom with a low diffusion coefficient potentially suitable for doping the channel of transistors. Systematic experiments are described which measure the susceptibility of indium to transient enhanced diffusion caused by ion implant damage introduced during the transistor fabrication process. We find that indium diffusion is dramatically enhanced by a source of interstitials and that the amount of enhancement is comparable to that seen for boron. Indium is preferable as a channel dopant not because of its diffusion behavior, but rather because a narrow ion implanted distribution can be obtained using the heavy indium ion, giving a more steeply retrograde profile than can be achieved by boron doping. These results help clarify the physics of indium and boron doping in small devices.

R-Capriccio: a capacity planning and anomaly detection tool for enterprise services with live workloads

As the complexity of IT systems increases, performance management and capacity planning become the largest and most difficult expenses to control. New methodologies and modeling techniques that explain large-system behavior and help predict their future performance are now needed to effectively tackle the emerging performance issues. With the multi-tier architecture paradigm becoming an industry standard for developing scalable client-server applications, it is important to design effective and accurate performance prediction models of multi-tier applications under an enterprise production environment and a real workload mix. To accurately answer performance questions for an existing production system with a real workload mix, we design and implement a new capacity planning and anomaly detection tool, called R-Capriccio, that is based on the following three components: i) a Workload Profiler that exploits locality in existing enterprise web workloads and extracts a small set of most popular, core client transactions responsible for the majority of client requests in the system; ii) a Regression-based Solver that is used for deriving the CPU demand of each core transaction on a given hardware; and iii) an Analytical Model that is based on a network of queues that models a multi-tier system. To validate R-Capriccio, we conduct a detailed case study using the access logs from two heterogeneous production servers that represent customized client accesses to a popular and actively used HP Open View Service Desk application.

EOS/ESD reliability of partially depleted SOI technology

A model for predicting the electrostatic discharge (ESD) protection level of PD-SOI MOSFETs and diodes is presented along with data to support the model. The form of the model is compatible with circuit simulators. An important design rule for layout of multifinger SOI ESD protection MOSFETs has been derived from the model. We present experimental data to support this design rule.

Scalability Of Plasma Damage With Gate Oxide Thickness

The effect of decreasing gate oxide thickness on the susceptibility to pre-metallization plasma damage is investigated for the range of 40-80A for both n and p type MOS capacitors. An antenna design, which intentionally uses an excessive number of contacts, has been used as a tool for excessive damage initiation to investigate the scalability of plasma damage with gate oxide thickness. Electrical reliability results indicate that susceptibility to damage increases with decreasing oxide thickness. Breakdown field was found to be an appropriate reliability criterion for comparing various oxide thicknesses.

Laser-Assisted TiSi 2 Formation for ULSI Applications

In this paper, we describe the results of recent work in which TiSi 2 formation on deep-submicron polysilicon gates is achieved using pulsed excimer laser irradiation. Formation of low resistivity titanium suicide on sub-0.1 μm polysilicon lines is confirmed by sheet resistance measurements. High-resolution TEM examination shows exceptionally smooth interface between suicide and heavily-doped silicon substrate. Gate to source/drain bridging is not observed. Analytical techniques including Rutherford backscattering spectroscopy (RBS) and X-ray diffraction (XRD) have been used to characterize the irradiated films. This laser-assisted suicide formation process is a promising technology for extreme submicron MOSFET applications.

Hydrogenated Amorphous Silicon Photodiode Technology for Advanced CMOS Active Pixel Sensor Imagers

Amorphous silicon photodiode technology is a very attractive option for image array integrated circuits because it enables large die-size reduction and higher light collection efficiency than c-Si arrays. We have developed a photodiode array technology that is fully compatible with a 0.35µm CMOS process to produce image sensors arrays with 10-bit dynamic range that are 30% smaller than comparable c-Si photodiode arrays. The VGA (640x480), array demonstrated here uses common intrinsic and p-type contact layers, and makes reliable contact to those layers by use of a monolithic transparent conductor strap tied to vias in the interconnect. The work presented here will discuss performance issues and solutions that lend themselves to cost-effective high-volume manufacturing. The various methods of interconnection of the diode to the array and their advantages will be presented. The photodiode dark leakage current density is about 80 pA/cm 2 , and its absolute quantum efficiency peaks about 85% at 550 nm. The effect of doped layer thickness and concentration on quantum efficiency, and the effect of a-Si:H defect concentration on diode performance will be discussed.

100-nm CMOS gates patterned with 3 sigma below 10 nm

We have developed a process that uses a series of depositions and etches to pattern poly-silicon gates, eliminating the component of line width variation that normally arises from photolithography. Because the depositions and etches that determine line width are well controlled, we can pattern finer lines with better control using this process than with conventional methods. The results presented here show 3(sigma) < 10 nm for 100 nm lines. They are consistent with requirements for patterning gates in 2006 according to the 1997 edition of the National Technology Roadmap for Semiconductors. Using this patterning technique, we have made 100 nm nMOS transistors with 2 nm thick gate oxide, operating at 1.3 V. The distributions of important variables that characterize the operation of these transistors are shown to be much tighter than we obtain with conventional lithography.

Investigation of the Need for Alternative cleaning Chemistries for 30Å Gate Oxides

A comparative study of pregate cleaning solution chemistries has been conducted, for 30A furnace oxides, to investigate the feasibility of continuing to use current cleaning technologies in this thickness range. The experiment focused on correlating changes of device properties with changes in chemistry. Several options were investigated for growing or etching the surface passivation oxide. Chemistries studied included standard SC1 (with Megasonic)/SC2, final HF, as well as room temperature single bath HF based chemistries (HF only, HF+H 2 O 2 , HF+HCl, HF+H 2 O 2 +HCl, SPM+HF). These chemistries were evaluated in terms of oxidation rate, metallic contamination from solutions, capacitance-voltage (CV) characteristics, and gate oxide integrity. Data suggest that furnace oxides can be reliably grown using conventional cleaning technology. HF-based mixtures might be justified for even more aggressive gate oxide thicknesses.