Amr M. Bayoumi

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Greens function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.

Scientific and Engineering Computing Using ATI Stream Technology

This continuing exploration of GPU technology examines ATI Stream technology and its use in scientific and engineering applications.

C-V and gate tunneling current characterization of ultra-thin gate oxide MOS (t/sub ox/=1.3-1.8 nm)

Direct tunneling of ultra-thin gate oxides results in exponential increases in gate leakage current (Lo et al, 1997). Moreover, the loss of inversion charge due to the carrier quantization then becomes significant. Hence, more physically accurate models are urgently needed. In this paper, an equivalent circuit approach considering the gate tunneling current as well as other QM effects is presented to characterize these phenomena for gate oxide thicknesses ranging from 1.3-1.8 nm.

Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures

Device model evaluation is one of the most time-consuming tasks in analog simulators such as SPICE. Graphics Processing Unit (GPU) architectures allow massive utilization of vector data on SIMD architectures. In this paper, the formulation of double precision device model equations into a form compatible with stream computing is presented. We show data on isolating typical bottlenecks, especially the communication and kernel call overheads. Our results indicate speedup of up to 20X when counting overheads, and up to 50X when using techniques to overcome these overheads. In particular, we show that our techniques are valid for small device counts, which is typically a well known problem for accelerated parallel computing with communications overheads.

Scalability Of Plasma Damage With Gate Oxide Thickness

The effect of decreasing gate oxide thickness on the susceptibility to pre-metallization plasma damage is investigated for the range of 40-80A for both n and p type MOS capacitors. An antenna design, which intentionally uses an excessive number of contacts, has been used as a tool for excessive damage initiation to investigate the scalability of plasma damage with gate oxide thickness. Electrical reliability results indicate that susceptibility to damage increases with decreasing oxide thickness. Breakdown field was found to be an appropriate reliability criterion for comparing various oxide thicknesses.

Parallel circuit simulation using the direct method on a heterogeneous cloud

This paper discusses the development of a parallel SPICE circuit simulator using the direct method on a cloud-based heterogeneous cluster, which includes multiple HPC compute nodes with multi-sockets, multicores, and GPUs. A simple model is derived to optimally partition the circuit between the compute nodes. The parallel simulator is divided into four major kernels: Partition Device Model Evaluation (PME), Partition Matrix Factorization (PMF), Interconnection Matrix Evaluation (IME), and Interconnection Matrix Factorization (IMF). Another model is derived to assign each of the kernels to the most suitable execution platform of the Amazon EC2 heterogeneous cloud. The partitioning approach using heterogeneous resources has achieved an order-of-magnitude speedup over optimized multithreaded implementations of SPICE using state of the art KLU and NICSLU packages for matrix solution.

Design and operation of a cluster-tool-based rapid thermal processing module

A cluster tool rapid thermal processing module for single wafer processing is described. The various design and actual implementation issues are discussed, together with the operational characteristics. The module is then evaluated as a low thermal budget tool for MOS gate stack formation. Film quality is electrically assessed.<<ETX>>

Analysis of Dual Gate Structures Using Double-Well and WKB Quantization Rules

An alternative method for direct calculation of energy levels for symmetric dual gate structures with body widths of 3-10 nm is presented in the current paper, using double well analysis and Wentzel-Kramers-Brillouin (WKB) quantization rules. The double well analysis explains the lower energy level splitting, as well as the twin shape of the corresponding wave function with odd-even symmetry. The potential is approximated using a parabolic potential. The perturbation analysis, which already gives good accuracy for higher energies and lower electron effective mass, is compared with the current approach. The combination of the double well and WKB method gives improved accuracy for energies below barrier maximum potential, over perturbation potential, while a simple analytic second-order WKB correction term is needed for energies just above the potential peak. Using the WKB representation of wave function, the effect of finite barrier height on wave function penetration and on energy levels is analytically treated, for all energy levels, with barriers as low as 0.5 eV. Theoretical models are verified using numerical eigenvalue/eigenvector solvers, while device modeling results are compared with self-consistent simulator.

Hardware implementation of LU decomposition using dataflow architecture on FPGA

Recent FPGA technology advances permitted the hardware implementation of selected software functions to enhance programs performance. Most of the work done was only concerned with integer operations. Little effort addressed floating point operations. In this paper we propose a dataflow implementation of the LU decomposition on FPGA. A modified Kernighan-Lin based task partitioning and assignment algorithm is presented in this paper. The algorithm showed acceptable improvement over existing techniques.

D2. Simplified analytical iterations for electron wavefunction using self-consistent solution for nm MOS gate stacks

In this paper, self consistent numerical solution of Poisson-Schrodinger equations is conducted using the shooting method, Numerovs integration, and damped Newton-Raphson iterative method, in order to obtain a reference electron distribution at high gate voltages for NMOS Metal gate/high-k stacks. The technology parameters are selected according to the ITRS roadmap for 22nm technologies, where a mid-gap metal gate is investigated. The results are compared to the using the analytical form of the Airy function envelope wavefunction, proposed in the literature as a solution for the first ground state. Instead of iterating over a very large number of points throughout the depletion region and inversion layer, only one analytical expression is solved using Newton-Raphson method, as a function of one fitting parameter. This procedure bypasses the numerical solution for discrete energy levels, and eliminates numerical integration needed to calculate charge and potential distributions in Poissons equation. Analytical expressions for the charge, electric field and potential distribution as a function of distance are developed as a function of just one parameter.