Carlos H. Díaz

Dynamic gate coupling of NMOS for efficient output ESD protection

A dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported. The authors discuss the gate coupling phenomenon for NMOS transistors and its effect under ESD transient conditions. A dynamic gate-coupled device was studied to understand the gate coupling effect. The authors present the complete phenomena and results for nonsilicided devices as well as for silicided structures. The measured ESD stress results are given. The gate coupling effect and device operation under ESD are explained by using modeling and simulation results. The design issues for optimum output ESD protection are also discussed.<<ETX>>

Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices

Previous work on electrothermal simulation using network analysis techniques has been of limited use due to the lack of avalanche breakdown modeling capability and the models to efficiently describe the temperature dynamics. Particularly, simulation of electrical overstress (EOS) and electrostatic discharge (ESD), which are important threats to IC reliability, require an accurate description of temperature-dependent device electrical behaviour including breakdown phenomenon. This paper presents electrothermal device models and their implementation in a new circuit-level electrothermal simulator iETSIM. Simulation results for an I/O protection device in an advanced MOS process are presented to demonstrate iETSIMs ability to accurately model device behaviour up to the onset of second breakdown. >

Building-in ESD/EOS reliability for sub-halfmicron CMOS processes

MOSFET design in high performance CMOS technologies is driven primarily by performance requirements and reliability issues such as hot carrier degradation. These requirements generally lead to processes that are inherently weak in terms of ESD and EOS. This paper presents a case of building-in ESD/EOS reliability through nMOSFET drain design for a 0.35 /spl mu/m CMOS process that compromises neither the performance nor the hot carrier reliability. Three process options were considered: nLDD or nDDD ESD implants, and a silicide-block option. The nDDD option for the I/O transistors was chosen as it complied with the performance and reliability (ESD and HCI) specifications and its implementation cost was lower than a silicide-block option. The paper presents data demonstrating the advantages of the nDDD solution over the other alternatives. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout parameters on ESD performance, and hot-carrier data are reviewed.

Bi-modal triggering for LVSCR ESD protection devices☆

Abstract This paper addresses three aspects of LVSCR protection devices namely, LVSCR layout optimization, triggering techniques, and the impact of stress signal slew-rate on ESD performance. Circuit techniques to achieve bi-modal triggering for LVSCR ESD protection schemes are presented. The low voltage trigger mode operates when the chip is in packaging and assembly while the high voltage mode operates when the chip is in the final product board with the power supplies applied. The triggering techniques discussed here are particularly useful in conjuction with high speed I/Os and interface ICs. The paper also reports the impact of stress slew rates on the failure thresholds. In particular, it is shown that when the slew rate is increased from 0.2 to 0.4 A/ns, the SCR failure threshold decreases from that given by a second breakdown failure mode to the one dictated by an early oxide failure. The paper concludes with an analysis of the LVSCR layout parameters on its trigger and ESD clamping effectiveness.

Electrical overstress and electrostatic discharge

Semiconductor devices have a limited ability to sustain electrical overstress (EOS). The device susceptibility to EOS increases as the device is scaled down to submicron feature size. At present, EOS is a major cause for IC failures. Published reports indicate that nearly 40% of IC failures can be attributed to EOS events. Hence, EOS threats must be considered early in the design process. For semiconductor devices, EOS embodies a broad range of electrical threats due to electromagnetic pulses, electrostatic discharge (ESD), system transients, and lightning. EOS-related failures in semiconductor devices can be classified according to their primary failure mechanisms into: thermally-induced failures, electromigration, electric-field-related failures. In general, thermally-induced failures are related to the doping level, junction depth, and device characteristic-dimensions whereas electric-field induced failures are primarily related to the breakdown of thin oxides in MOS devices. >

Modeling of electrical overstress in integrated circuits

List of Figures. List of Tables. Preface. 1. Electrical Overstress in ICs. 2. NMOS ESD Protection Devices and Process Related Issues. 3. Measuring EOS Robustness in ICs. 4. EOS Thermal Failure Simulation for Integrated Circuits. 5. ITSIM: a Nonlinear 2D--1D Thermal Simulator. 6. 2D Electrothermal Analysis of Device Failure in MOS Processes. 7. Circuit Level Electrothermal Simulation. 8. IETSIM: an Electrothermal Circuit Simulator. 9. Summary and Future Research. Bibliography. Index.

Electrical overstress (EOS) power profiles: A guideline to qualify EOS hardness of semiconductor devices

Abstract We propose the power-to-failure vs. time-to-failure relationship (power profile) as a measure to determine the EOS hardness of integrated circuits. Bipolar integrated circuits with different I/O ESD protection designs were characterized for HBM-ESD and EOS under unipolar stress conditions. Measured power profiles indicate that good ESD performance is not a sufficient condition to assure EOS robustness. Furthermore, experimentally measured power profiles together with failure analysis techniques can pinpoint layout design weaknesses.

New algorithms for circuit simulation of device breakdown

Numerical algorithms that enable extension of device models into avalanche breakdown region without disturbing the convergence of modified nodal-analysis-based circuit simulators are introduced. Details of model implementation into circuit simulators are presented along with applications. In particular, circuit-level simulation of nondestructive electrostatic discharge phenomena is discussed along with the time-step size on the simulation of negative resistance structures. >

Studies of EOS susceptibility in 0.6 μm nMOS ESD I/O protection structures

Abstract The electrical overstress (EOS) susceptibility of ESD I/O protection structures needs to be investigated to assure overall EOS/ESD reliability in advanced processes. In this paper, the EOS resistance of 0.6 μm nMOS ESD protection structures is analyzed in terms of experimental data, failure analysis results and, device-level electrothermal simulations. Thermally induced EOS failures are explained in terms of physical phenomena leading to thermal runaway. Device width and contact-to-gate spacing are shown to directly affect the EOS robustness of the protection devices.

EOS/ESD reliability of partially depleted SOI technology

A model for predicting the electrostatic discharge (ESD) protection level of PD-SOI MOSFETs and diodes is presented along with data to support the model. The form of the model is compatible with circuit simulators. An important design rule for layout of multifinger SOI ESD protection MOSFETs has been derived from the model. We present experimental data to support this design rule.