Yung-Shou Cheng

Design of Microstrip-to-Microstrip Via Transition in Multilayered LTCC for Frequencies up to 67 GHz

A wide-band microstrip-to-microstrip via transition proposed for connecting an integrated circuit chip and an antenna array on the opposite sides of a multilayered low-temperature co-fired ceramic substrate is investigated in this paper. To facilitate the design, it is decomposed into external and internal segments, which consist of two microstrip-to-via transitions and a multilayered through-hole via with four ground vias, respectively. The equivalent impedance of the internal segment is carefully calculated from the lump-circuit model extracted by Ansoft Q3D, and verified by high-frequency structure simulation (HFSS). The S-parameters of external segments are simulated by HFSS for impedance matching, thereby obtaining the appropriate physical parameters. The physical mechanisms that result in the insertion loss are explored in detail, and the effects of via diameter are also investigated for the reduction of insertion loss. By combining the designs of the external and internal segments, the simulated S-parameters demonstrated that the overall return loss level was above 20 dB within 57-67 GHz spectrum and insertion loss was better than 0.48 dB from d.c. up to 67 GHz. Coherent results between simulation and measurement were also obtained with a back-to-back transition structure.

Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.

Fewest vias design for microstrip guard trace by using overlying dielectric

The unwanted ringing noise owing to the resonance related to the spacing of shorting vias on microstrip guard traces might degrade the signal quality of adjacent interconnects. This paper proposes a novel design method to reduce the ringing noise by overlying a thin dielectric with higher dielectric constant onto the original microstrip substrate. It has the advantages of minimizing the required number of shorting vias and achieving less restricted circuit routing.

Direct Eye Diagram Optimization for Arbitrary Transmission Lines Using FIR Filter

A new design algorithm, which directly optimizes the eye diagram using the finite impulse response (FIR) filter as transmitter pre-emphasis, is proposed to counteract the intersymbol interference (ISI) in the high-speed data transmission. To start with, this paper presents a fast eye diagram analysis which relates to the step response of the transmission line system. It is found that not only the frequency-dependent loss but also the multiple reflections due to impedance mismatch contribute much to ISI. A systematic method is then proposed to efficiently design FIR filter for best eye diagram improvement. The optimal set of tap coefficients and tap numbers are determined by direct search method according to the required specifications on eye mask for different applications. Subsequently, the equalization results for unterminated and lossy lines are given to demonstrate the remarkable mitigation of the ISI effects incurred by multiple reflections and frequency-dependent loss. Experimental results are also presented to validate the efficiency of the proposed method.

Enhanced Microstrip Guard Trace for Ringing Noise Suppression Using a Dielectric Superstrate

Grounded guard traces are increasingly used to reduce the coupling-induced crosstalk, but the incurred ringing noise will strongly limit the performance for the microstrip structures. This paper describes the generation mechanism of the ringing noise and derives an analytical formula of the noise magnitude. Besides, an enhanced microstrip guard trace design is proposed to eliminate the ringing noise by covering the original microstrip structure with a superstrate of higher permittivity. A design space versus the superstrate thickness and the dielectric constant are constructed and in which, the guard trace needs be grounded at the two ends only without causing any ringing noise. Finally, the time-domain simulations and experiments are performed to verify the proposed concept.

SI-aware layout and equalizer design to enhance performance of high-speed links in blade servers

With increasing demand on higher performance for high speed I/O links, the signal integrity-aware layout schemes and equalization have been attributed as the critical techniques to improve the eye diagram. This paper describes a synthetic design to enhance the system performance and its application to realistic high-speed blade servers. Simulation results are provided to validate the design concept, demonstrating significant improvement in eye height and width by 284% and 96.7%, respectively, for a SATA II link of 1.175m length and 3 Gb/s data rate.

Fast Prediction and Optimal Design for Eye-Height Performance of Mismatched Transmission Lines

As the data rate becomes higher, the intersymbol interference influences the signal quality more seriously. In this paper, a simple methodology is presented to predict eye height for general transmission line systems with mismatched source and load terminations. Simple formulas are derived to estimate the eye height with the consideration of the reflection coefficients at both ends, the loss constant, and a matched pulse response of the transmission line for the cases of long and short transmission lines. Furthermore, a contour map is successfully constructed to represent the variations of eye height versus the reflection coefficients and used to facilitate the termination design for the best signal integrity performance. Finally, the time domain simulations and experiments are also provided to verify the proposed methodology.

Enhanced eye-height estimation of mismatched lossy transmission lines

A simple formula is derived to estimate the worst-case eye height for mismatched transmission line systems, using system pulse response and the idea of peak distortion analysis. A contour map which represents eye height variations for different reflection coefficients at the drivers and receivers is constructed and used to facilitate the driver and termination designs for the best eye diagram performance. Subsequently, the eye diagram results for two different mismatched transmission lines are given to validate the accuracy of the presented contour map.

Optimization of FIR filter to improve eye diagram for general transmission line systems

The finite-impulse response (FIR) filter technique has been widely used for pre-emphasis of channels to mitigate the intersymbol interference (ISI) resulted from both frequency dependent losses and reflections. This paper proposes a systematic methodology, based on arbitrary step response, to determine the tap setting of multi-tap FIR filter for best eye diagram improvement. The required tap number and the optimal tap coefficients are determined according to the compensation efficiency and hence the ultimate performance of FIR filter is evaluated. Eventually, the compensation results for two specific 5Gbps signalling systems, which include significant effects of losses and multiple reflections are demonstrated to validate the optimization method.

A wide-band microstrip-to-microstrip multi-layered via transition using LTCC technology

A wide-band microstrip-to-microstrip via transition used for connecting integrated circuits and antenna array in a multi-layered low-temperature co-fired ceramic substrate is investigated in this paper. The via transition is decomposed into external and internal segments to facilitate the design. The equivalent impedance of internal segment, consisting of multi-layered through-hole via with four ground vias, is calculated from the lump-circuit model generated by Ansoft Q3D Extractor. The electrical performance of the external segment, consisting of via to microstrip lines, is evaluated by the microstrip-to-coax transition to choose appropriate via physical parameters. Finally, the geometrical parameters of entire transition are obtained by combining the results of the external and internal segments. It has been demonstrated, through the simulation results by commercial software Ansoft HFSS, that the return loss is better than 19dB over a band from DC up to 70GHz with an in-band insertion loss better than 0.48dB.