Daewon Ha

Sub-20 nm CMOS FinFET technologies

A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.

Extremely scaled silicon nano-CMOS devices

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

Observation of bulk HfO2 defects by spectroscopic ellipsometry

Spectroscopic ellipsometry was used to investigate the oxidation of pure Hf films on silicon for the formation of HfO2 (hafnium oxide) gate-dielectric films in advanced complementary metal-oxide-semiconductor field-effect transistors. Absorption coefficients near the absorption edge were extracted using the data inversion method, in which the optical constants for short wavelengths were calculated using the film thickness determined from long-wavelength data. The extracted optical band gap of 5.7 eV matches well with published data, and a curve shift due to crystallization was detected. In addition, an extra absorption peak corresponding to electron transition from the valence band to a defect energy level was observed in the range 4.5–5.0 eV above the valence-band edge. The 1.2 eV energy difference between the conduction-band edge and the edge of this extra peak is close to the electron trap energy level reported elsewhere. The intensity of the detected peak was clearly correlated with leakage current an...

FinFET process refinements for improved mobility and gate work function engineering

Process refinements to improve the performance of FinFETs are described. Hydrogen annealing is shown to provide high surface quality on etched fin sidewalls for improved drive current and noise performance. Appropriate V/sub t/ is achieved in lightly doped p-channel FinFETs using Molybdenum (Mo) as the gate-electrode material for the first time. Multiple values of V/sub t/ are achieved via gate work function engineering by selective implantation of Mo.

Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs

Gate-induced drain leakage (GIDL) current is investigated in single-gate (SG) ultra-thin body field effect transistor (FET), symmetrical double-gate (DG) FinFET, and asymmetrical DG metal oxide semiconductor field effect transistor (MOSFET) devices. Measured reductions in GIDL current for SG and DG thin-body devices are reported for the first time. The thin-body devices exhibit much lower GIDL current than bulk-Si MOSFETs, and the GIDL is found to decrease with decreasing body thickness. These results can be explained by the reduction in transverse electric field at the surface of the drain and the increase in transverse effective mass with decreasing body thickness.

Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs

The hydrogen annealing process has been used to improve surface roughness of the Si-fin in CMOS FinFETs for the first time. Hydrogen annealing was performed after Si-fin etch and before gate oxidation. As a result, increased saturation current with a lowered threshold voltage and a decreased low-frequency noise level over the entire range of drain current have been attained. The low-frequency noise characteristics indicate that the oxide trap density is reduced by a factor of 3 due to annealing. These results suggest that hydrogen annealing is very effective for improving device performance and for attaining a high-quality surface of the etched Si-fin.

Reliability study of CMOS FinFETs

Hot-carrier and oxide reliability of CMOS FinFETs with 2.1 nm-thick gate-SiO/sub 2/ were investigated. It was found that hot-carrier immunity improves as the fin width (body thickness) decreases, which facilitates gate-length scaling, while it is degraded at elevated temperature due to the self-heating effect. High values of Q/sub BD/ are achieved for devices with very small gate area. A post-fin-etch hydrogen anneal is helpful for improving hot-carrier immunity and Q/sub BD/.

Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain

Nanoscale ultrathin body (UTB) p-channel MOSFETs with body thickness down to 4 nm and raised source and drain (S/D) using selectively deposited Ge are demonstrated for the first time. Devices with gate length down to 30 nm show high drive current, low off current, and excellent short-channel behavior. Mobility enhancement and threshold-voltage shift due to the quantum confinement of inversion charge in the ultrathin body are investigated.

Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs

Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully depleted silicon-on-insulator ( devices such as the ultrathin body (UTB) MOSFET and double-gate FinFET. A plasma charge trap effectively eliminates high-energy particle bombardment during Mo sputtering; hence the gate-dielectric integrity (TDDB, Q/sub BD/) is significantly improved and the field-effect mobility in Mo-gated MOSFETs follows the universal mobility curve. The effects of etch process parameters such as chlorine (Cl/sub 2/) and oxygen (O/sub 2/) gas flow rate, and source and bias radio frequence powers, were investigated in order to optimize the Mo etch rate and selectivity to SiO/sub 2/. A highly selective etch process was successfully applied to pattern Mo gate electrodes for UTB MOSFETs and FinFETs without leaving any residue or stringers. Measured electrical characteristics and physical analysis results are discussed.

Tunable work function molybdenum gate technology for FDSOI-CMOS

A simple technique for tuning the work function of molybdenum (Mo) gate material over a wide range (4.5 V-4.9 V) is investigated. Ultra-low energy (/spl les/3 keV) Ar/sup +/ and N/sup +/ ion implantation is used to selectively induce structural and/or chemical changes in Mo gate films. These changes are shown to directly affect the Mo gate work function, so that it can be adjusted by adjusting the implant parameters and annealing conditions. The mechanism behind this phenomenon is investigated using X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS). The applicability of this technique for threshold voltage (V/sub TH/) control, particularly in fully-depleted SOI CMOS devices, is demonstrated with Mo gated ultra-thin body (UTB) SOI MOSFETs and double-gate FinFETs.