Weiping Shi

K longest paths per gate (KLPG) test generation for scan-based sequential circuits

To detect the smallest delay faults at a fault site, the longest path(s) through it must be tested at full speed. Existing test generation tools are inefficient in automatically identifying the longest testable paths due to the high computational complexity. In this work a test generation methodology for scan-based synchronous sequential circuits is presented, under two at-speed test strategies used in industry. The two strategies are compared and the test generation efficiency is evaluated on ISCAS89 benchmark circuits and industrial designs. Experiments show that testing transition faults through the longest paths can be done in reasonable test set size.

A fast hierarchical algorithm for 3-D capacitance extraction

We presen t a new algorithm for computing the capacitance of three-dimensional perfect electrical conductors of complex structures. The new algorithm is significantly faster and uses muc h less memory than previous best algorithms, and is kernel independent. The new algorithm is based on a hierarchical algorithm for the <italic>n</italic>-body problem, and is an acceleration of the boundary-element method for solving the integral equation associated with the capacitance extraction problem. The algorithm first adaptively subdivides the conductor surfaces into panels according to an estimation of the potential coefficients and a user-supplied error band. The algorithm stores the poten tial coefficient matrix in a hierarchical data structure of size <italic>O</italic>(<italic>n</italic>), although the matrix is size <italic>n</italic><supscrpt>2</supscrpt> if expanded explicitly, where<italic>n</italic> is the n umber of panels. The hierarchical data structure allows us to multiply the coefficient matrix with an y vector in <italic>O</italic>(<italic>n</italic>) time. Finally, w e use a generalized minimal residual algorithm to solve <italic>m</italic> linear systems each of size <italic>n</italic> × <italic>n</italic> in <italic>O</italic>(<italic>mn</italic>) time, where <italic>m</italic> is the n umber of conductors. The new algorithm is implemented and the performance is compared with previous best algorithms. F or the <italic>k</italic> × <italic>k</italic> bus example, our algorithm is 100 to 40 times faster than F astCap, and uses 1/100 to 1/60 of the memory used by F astCap. The results computed by the new algorithm are within 2.7% from that computed by FastCap.

A fast hierarchical algorithm for three-dimensional capacitance extraction

The authors present a new algorithm for computing the capacitance of three-dimensional electrical conductors of complex structures. The new algorithm is significantly faster and uses much less memory than previous best algorithms and is kernel independent. The new algorithm is based on a hierarchical algorithm for the n-body problem and is an acceleration of the boundary element method (BEM) for solving the integral equation associated with the capacitance extraction problem. The algorithm first adaptively subdivides the conductor surfaces into panels according to an estimation of the potential coefficients and a user-supplied error bound. The algorithm stores the potential coefficient matrix in a hierarchical data structure of size O(n), although the matrix is size n/sup 2/ if expanded explicitly, where n is the number of panels. The hierarchical data structure allows the multiplication of the coefficient matrix with any vector in O (n) time. Finally, a generalized minimal residual algorithm is used to solve m linear systems each of size n /spl times/ n in O(mn) time, where m is the number of conductors. The new algorithm is implemented and the performance is compared with previous best algorithms for the k /spl times/ k bus example. The new algorithm is 60 times faster than FastCap and uses 1/80 of the memory used by FastCap. The results computed by the new algorithm are within 2.5% from that computed by FastCap. The new algorithm is 5 to 150 times faster than the commercial software QuickCap with the same accuracy.

Fast Algorithms for Slew-Constrained Minimum Cost Buffering

As a prevalent constraint, sharp slew rate is often required in circuit design, which causes a huge demand for buffering resources. This problem requires ultrafast buffering techniques to handle large volume of nets while also minimizing buffering cost. This problem is intensively studied in this paper. First, a highly efficient algorithm based on dynamic programming is proposed to optimally solve slew buffering with discrete buffer locations. Second, a new algorithm using the maximum matching technique is developed to handle the difficult cases in which no assumption is made on buffer input slew. Third, an adaptive buffer selection approach is proposed to efficiently handle slew buffering with continuous buffer locations. Fourth, buffer blockage avoidance is handled, which makes the algorithms ready for practical use. Experiments on industrial netlists demonstrate that our algorithms are very effective and highly efficient: we achieve about 90x speedup and save up to 20% buffer area over the commonly used van Ginneken style buffering. The new algorithms also significantly outperform previous works that indirectly address the slew buffering problem.

A fast algorithm for optimal buffer insertion

The classic buffer insertion algorithm of van Ginneken has time and space complexity O(n/sup 2/), where n is the number of possible buffer positions. For more than a decade, van Ginnekens algorithm has been the foundation of buffer insertion. In this paper, we present a new algorithm that computes the same optimal buffer insertion, but runs much faster. For 2-pin nets, our time complexity is O(nlogn) and space complexity is O(n). For multipin nets, our time complexity is O(nlog/sup 2/n) and space complexity is O(nlogn). The speedup is achieved by four novel techniques: predictive pruning, candidate tree, fast redundancy check, and fast merging. On industrial test cases, the new algorithms is 2-80 times faster than van Ginnekens algorithm and uses 1/4-1/500 of the memory. Since van Ginnekens algorithm and its variations are used by most existing algorithms on buffer insertion and buffer sizing, our new algorithm significantly improves the performance of all these algorithms. The predictive pruning technique has been applied to buffer cost minimization (Shi et al., 2004), and significantly improved the running time.

Longest path selection for delay test under process variation

Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay among all paths through that fault site. There are often multiple longest paths for each fault site in the circuit, due to different process conditions. To detect the smallest delay fault, it is necessary to test all longest paths through the fault site. However, previous methods are either inefficient or their results include too many paths that are not longest.This paper presents an efficient method to generate the longest path set for delay test under process variation. To capture both structural and systematic process correlation, we use linear delay functions to express path delays under process variation. A novel path-pruning technique is proposed to discard paths that are not longest, resulting in a significantly reduction in the number of paths compared with the previous best method. The new method can be applied to any process variation as long as its impact on delay is linear.

Optimal interconnect diagnosis of wiring networks

Interconnect diagnosis is an important problem in very large scale integration (VLSI), multichip module (MCM) and printed circuit board (PCB) production. The problem is to detect and locate all the shorts, opens and stuck-at faults among a set of nets using the minimum number of parallel tests. In this paper, we present worst-case optimal algorithms and lower bounds to several open problems in interconnect diagnosis. >

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects

Even with the wide adaptation of resolution enhancement techniques in sub-wavelength lithography, the geometry of the fabricated interconnect is still quite different from the drawn one. Existing layout parasitic extraction (LPE) tools assume perfect geometry, thus introducing significant error in the extracted parasitic models, which in turn cases significant error in timing verification and signal integrity analysis. Our simulation shows that the RC parasitics extracted from perfect GDS-II geometry can be as much as 20% different from those extracted from the post litho/etching simulation geometry. This paper presents a new LPE methodology and related fast algorithms for interconnect parasitic extraction under photolithographic effects. Our methodology is compatible with the existing design flow. Experimental results show that the proposed methods are accurate and efficient.

A circuit level fault model for resistive opens and bridges

Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are modeled. In this paper, we propose a circuit level model for resistive open and bridge faults. All possible fault behaviors are illustrated and a general resistive bridge delay calculation method is proposed. The new models are practical and easy to use. Fault simulation results show that the new models help the delay test to catch more bridge faults.

An O(nlogn) time algorithm for optimal buffer insertion

The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity <i>O(n²)</i>, where <i>n</i> is the number of possible buffer positions.