Wen Jia

Fetal heart rate monitoring system with mobile internet

The fetal heart rate is vital for monitoring fetal well-being. Fetal heart rate monitoring based on acoustic techniques is passive and noninvasive. In this work, a fetal heart rate monitoring system based on phonocardiographic method is proposed. A portable low-power stethoscope is customized which meets the need for sensitivity in the monitoring. A noise cancellation method and adaptive matching method are applied to extract the fetal heart rate effectively. Clinical trials are carried out on pregnant women, and the comparison of fetal heart rates given by the proposed system with those given by the Doppler monitor is given to show the accuracy.

A 10 Mb/s hybrid two-point modulator with front-end phase selection and dual-path DCO modulation

This paper presents a hybrid two-point modulator for high data rate modulation. The two-point modulator utilizes a phase selection circuit with a high-frequency ΔΣ modulator (DSM) in low-pass modulation to achieve fine resolution for delay mismatch calibration. For high-pass modulation, a separate multi-bit path is designed for a digitally-controlled oscillator (DCO) in addition to the loop control path. A finite impulse response (FIR) filter is introduced in the high-pass modulation path to suppress quantization noise, while offering time-interleaving operation to mitigate the DCO sensitivity for each switching time. The proposed modulator is implemented in 65nm CMOS. Experimental results show that the modulator can achieve 10Mb/s GFSK modulation with the fine time resolution of 138ps.

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor

This paper proposes a mixed-level simulator for dynamic coarse-grained reconfigurable processor (CGRP), called ReSSIM (reconfigurable system simulation implementation mechanism), and the corresponding simulation tool-chain, including task compiler, profiler and debugger. A generic modeling methodology supporting convenient extension of on-chip modules is also proposed. In order to explore the details of the interested modules while maintaining reasonable simulation speed, RCA (reconfigurable computing array), the key reconfigurable device in ReSSIM, is modeled on cycle-accurate level, while the other modules are modeled on transaction level. The typical parameters of RCA are scalable and adjustable, which helps the architects to explore the massive details of the reconfigurable device. Experiment shows that simulation speedup achieved ranges from 9.26× to 18.39× compared with VCS (Synopsys verilog compiler simulator) when running three computingintensive kernel tasks of H.264 decoding algorithm—IDCT (inverse discrete cosine transform), deblocking and MC-chroma (motion compensation). Simulation speed for a set of real applications, such as MPEG4, G.729 and EFR, is 35× slower than the corresponding native executions (i.e. measured from the real chip). And the relative simulation errors are 11% less than the measured IPC (instructions per cycle) of the real chip.

Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC

Computing-intensive algorithms which occupy most of executing time are always the main bottleneck in real-time or high quality video applications. In this paper, the optimization methods of the computing-intensive decoding algorithms of H.264, including MC (Motion Compensation), Deblocking and IDCT-IQ (Inverse Discrete Cosine Transform — Inverse Quantization), are proposed firstly, and then implemented on the REMUS (REconfigurable MUltimedia System) which is an embedded coarse-grain reconfigurable multimedia system. Tests show that the efficiency of MC is improved by 32.5%, Deblocking by 69% and IDCT-IQ by 88.5% compared with XPP PACT(a commercial reconfigurable processor). Compared with typical ASIC solutions, execution performance of MC and IDCT improved by 49% and 17%, respectively, while that of Deblocking remained about the same.

A fast complete deblocking filter on a coarse-grained reconfigurable processor supporting H.264 high profile decoding

This paper implements a fast complete deblocking filter on a novel coarse-grained reconfigurable processor, REMUS (REconfigurable Multimedia System). Reconfigurable processors have been proved to be the potential candidates for multimedia processing. However, their weakness in processing control-intensive tasks becomes a bottleneck in many reconfigurable applications. Mapping control-intensive tasks onto coarse-grained reconfigurable processors efficiently will advance relevant researches significantly. This paper proposes several methods and techniques to achieve this goal. With the proposed methods and techniques, the deblocking process, which represents one of the most control-intensive tasks in an H.264/AVC video decoder, consumes only 306 clock cycles per macroblock on REMUS. Comparing to the deblocking filters on ADRES [4], FloRA [3], and XPP-III [2], the deblocking filer on REMUS by this work achieves the speedup of 66.74%, 85.83%, and 55.52%, respectively. The implementing methods and techniques can also be extended into other applications.

A wireless image acquisition system for artificial knee implant surgeries

A wireless image acquisition system has been proposed and implemented to improve the surgery quality of total knee arthroplasty (TKA) by providing direct images inside the artificial knee implants. The system consists of an image sensing device, a wireless data logger and the image display workstation. The sensing device has the identical dimension and size as the real spacer part in the implants. It is inserted into the knee implant to take the inside images. It is connected with the external data logger through a 432MHz wireless link. Circuit design details for the sensing device as well as the entire system will be discussed. Image processing methods to enhance the image quality under the specific extremely-low luminance environment will be presented.

A High-Voltage High-PSRR Power Management Circuit for BMS chip of new energy vehicle

This paper presents a High-Voltage High-PSRR (HVHP) power management circuit used in high-precision battery parameters acquisition chip for Battery Management System for new energy vehicles. It consists of a pre-regulator, a high PSRR (power supply rejection ratio) self-regulated bandgap voltage reference (BGR), high voltage linear regulator, with the capability of soft start, over current detect, and power-on reset generation. The Power Management Circuit has been designed in ASMCs 0.5µm HV60 BCD automotive electronics technology. Post-layout simulation result shows it can work under input voltage from 5.5V to 40V, and deliver a current up to 20mA. BGR has a very high PSRR of −125dB@1KHz and with the regulated voltage −100dB@1KHz. This design is applicable for BMS chip and has already been taped out.

A 0.5mW 1Mb/s multi-channel chirp-UWB transmitter with burst-mode transmission and optimized digital gradient

This paper presents a low power multi-channel chirp-UWB (C-UWB) transmitter for short range communication systems. The C-UWB transmitter generates a wideband FM signal with a steep spectral roll-off, while enabling a duty-cycled operation. To achieve an optimum duty-cycle control, burst-mode transmission and steep digital gradient generation techniques are employed. A 5-to-9GHz C-UWB transmitter is implemented in 65nm CMOS for multi-channel operation with a channel bandwidth of 500MHz. The transmitter achieves 1Mb/s data rate, consuming 0.5mW from a 1V supply.

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path

This paper describes an effective way of relaxing the nonlinearity problem of the digitally-controlled oscillator (DCO) in the two-point modulator design. A separate coarse varactor array dedicated for the high-pass modulation significantly simplifies the nonlinearity calibration of the DCO with a few-bit control. In addition, a finite-impulse response (FIR) filter is designed for the multi-bit high-pass modulation path to reduce the quantization noise, while offering a time-interleaving operation to minimize the DCO sensitivity to the coupling during switching time. A two-point modulator based on a semidigital fractional-N phase-locked loop (PLL) is implemented in 0.18μm CMOS. Simulation results show that the proposed modulator can achieve 10Mb/s GFSK/GMSK modulations with the EVM of -37dB.

A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS

A source-synchronous serial link receiver with an adaptive quarter-rate 2-tap DFE and a baud-rate CDR is demonstrated. The data-sampler-lane (DSL) of the DFE uses the combination of the soft-decision technique and a new dynamic structure to achieve a power efficiency of 0.24mW/Gb/s. The error-sampler-lane (ESL) based on the same dynamic structure is shared by the DFE adaption logic and baud-rate CDR logic to save power and area. A hybrid alternate clock scheme is implemented to satisfy the timing requirement and reduce power consumption further. This receiver fabricated in 65nm CMOS operates from 15 to 28Gb/s, and compensates for a Nyquist channel loss of 32dB with 0.42UI timing margin at 25Gb/s for BER=10-12. The active area is 0.18mm2 and the power consumption is 48mW at 25Gb/s from a 1.2V supply.