Hanjun Jiang

An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications

An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC

This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO

This paper presents a low-power transceiver with a reconfigurable sliding-IF (intermediate frequency) architecture targeted for wireless body area networks hubs covering 400 MHz and 2.4 GHz bands. By using this architecture, a 1608-1988 MHz PLL synthesizer with only 21% tuning range can fully cover all the available bands around 400 MHz and 2.4 GHz as defined by IEEE 802.15.6 NB (narrow band) and ZigBee. The dual-band transceiver has been designed in 0.18 μm CMOS process. The design consists of a receiver with a wideband front-end and a reconfigurable amplifier-mixer, a transmitter with a reconfigurable two stage full quadrature mixer, a ΣΔ fractional-N PLL and some auxiliary circuits. The measurement result has demonstrated that the proposed transceiver can satisfy the dual-band requirements with comparable or even better performance in noise, receiver sensitivity and power consumption compared to previously-reported transceivers for only a single band.

A wireless capsule endoscopic system with a low-power controlling and processing ASIC

This paper presents the design of a wireless capsule endoscopic system with a low-power controlling and processing ASIC. The system aims at several design challenges including system power reduction, system miniaturization and wireless wake-up method. These challenges are met by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology, and occupies a die area of 3.4 mm*3.3 mm. The digital core can work under a power supply down to 0.95V, and the power consumption is only 1.3 mW. The wireless capsule endoscope prototype has been implemented with this ASIC.

Testing High-Resolution ADCs With Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACs

This paper presents a deterministic dynamic element matching (DDEM) approach, which is applied to low-precision digital-to-analog converters (DACs) to generate uniformly spaced voltage samples for analog-to-digital converter (ADC) testing. Theoretical analysis is provided to show the test performance using this DDEM DAC. Both simulation results and experimental results from a fabricated DDEM DAC are presented to verify the performance. The ADC testing performance, by using an 8-bit DDEM DAC (linearity less than 5 bits without DDEM), is comparable to the best results reported in the literature using on-chip linear ramp generators. The DDEM technique offers great potential for use in both production test and built-in-self-test (BIST) environments.

An energy efficient implementation of on-demand MAC protocol in medical Wireless Body Sensor Networks

This paper presents an energy-efficient implementation of a real-time on-demand MAC protocol for medical Wireless Body Sensor Network (WBSN). Medical WBSN is focused on pervasive healthcare and medical applications, such as monitoring vital signs, making basic drug delivery, etc. The sensor nodes in the heterogeneous WBSN generally require different data rates, due to their differing functions. Additionally, because of the strict resource constraints, the sensor nodes must be ultra-low-power. Thirdly, low-rate treatment-function nodes must also “work-on-demand” to prove proper activities in the slave nodes such as stimulus and drug delivery. These three requirements cannot currently be satisfied simultaneously in commonly-used single channel implementations because the channel monitoring consumes too much power for long-term use. In the proposed implementation, a secondary channel is introduced in, which is used for channel listening only. Benefiting from the secondary channel, the node can achieve both real-time “work-on-demand” and zero idle power, by means of recovering energy from the “demand token”. An elaborated energy-harvesting RF module achieves monitoring the secondary channel. The prototype system of sensor nodes is expected for the zero-idle-power and the response time of less than 2ms.

Testing high resolution ADCs with low resolution/accuracy deterministic dynamic element matched DACs

This work presents a deterministic dynamic element matching (DDEM) approach which is applied to low precision DACs to generate stimulus signals for ADC testing. Both simulation results and experimental results from a fabricated DDEM DAC are presented to verify the performance. The ADC testing performance of an 8-bit DDEM DAC (linearity less than 5 bits without DDEM) is comparable to or better than the best results reported in the literature using on-chip linear ramp generators. The DDEM technique offers great potential for use in both production test and built-in-self-test(BIST) environments.

A SoC with 3.9mW 3Mbps UHF transmitter and 240μW MCU for capsule endoscope with bidirectional communication

An ultra-low-power system-on-a-chip (SoC) for wireless capsule endoscopes has been implemented, providing bidirectional communication between the capsule and the external data logger. The SoC is composed of a programmable UHF band transceiver with 3Mbps MSK transmitting and 64kbps OOK receiving, a 1.2V MCU with a dedicated image compressor, multiple on-chip voltage regulators, and etc. The SoC can work with a power supply down to 2.5V. The 3Mbps transmitter working at 400MHz band consumes only 3.9mW power, and the MCU draws only 200μΑ current from 1.2V supply. Fabricated in 0.18μm CMOS, the SoC occupies a die area of 13.3mm2 including the I/O pads. A capsule endoscope prototype has been developed using this SoC plus an image sensor. With this SoC, the capsule endoscope can capture 512∗512 gastrointestinal images with a frame rate of up to 3 fps.

A deterministic dynamic element matching approach for testing high-resolution ADCs with low-accuracy excitations

Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of Sigma-Delta structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digital-to-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and time-local nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement

Optimal loop parameter design of charge pump PLLs for jitter transfer characteristic optimization

An optimal loop parameter design method of charge pump PLLs for jitter transfer characteristic optimization is proposed. Based on the linear model of charge pump PLLs, the relationship between a PLLs loop parameters and jitter transfer characteristic is illustrated. Using the proposed optimal design method, a design example is given and the expected simulation result is obtained.