Wen-Jie Qi

Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric

Electrical and reliability properties of ultrathin HfO/sub 2/ have been investigated. Pt electroded MOS capacitors with HfO/sub 2/ gate dielectric (physical thickness /spl sim/45-135 /spl Aring/ and equivalent oxide thickness /spl sim/13.5-25 /spl Aring/) were fabricated. HfO/sub 2/ was deposited using reactive sputtering of a Hf target with O/sub 2/ modulation technique. The leakage current of the 45 /spl Aring/ HfO/sub 2/ sample was about 1/spl times/10/sup -4/ A/cm/sup 2/ at +1.0 V with a breakdown field /spl sim/8.5 MV/cm. Hysteresis was <100 mV after 500/spl deg/C annealing in N/sub 2/ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO/sub 2/ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V/sub DD/=2.0 V.

Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application

Physical, electrical and reliability characteristics of ultra thin HfO/sub 2/ as an alternative gate dielectric were studied for the first time. Crucial process parameters of oxygen modulated dc magnetron sputtering were optimized to achieve an equivalent oxide thickness (EOT) of 11.5 /spl Aring/ without deducting the quantum mechanical effect. Leakage current was 3/spl times/10/sup -2/ A/cm/sup 2/ at +1 V. Excellent dielectric properties such as high dielectric constant, low leakage current, good thermal stability, negligible dispersion and good reliability were demonstrated.

MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si

MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si have been investigated. Thin equivalent oxide thickness (EOT), low leakage, negligible frequency dispersion, interface density less than 10/sup 11/ cm/sup -2/ eV/sup -1/, small hysteresis, excellent reliability characteristics have been demonstrated. The ZrO/sub 2/ film has been shown to be amorphous. A thin interfacial Zr-silicate layer (k>8) exists and is beneficial in maintaining good interfacial quality. This Zr-silicate layer grows after annealing and can be minimized through process optimization. Well-behaved p-channel MOS transistor characteristics with a subthreshold swing of 80 mV/decade have also been achieved.

MOSFET devices with polysilicon on single-layer HfO/sub 2/ high-K dielectrics

MOSFETs and MOSCAPs of a single-layer thin HfO/sub 2/ gate dielectric with dual polysilicon gate were fabricated with self-aligned process and characterized. Polysilicon and dopant activation processes were optimized such that leakage current and equivalent oxide thickness (EOT) of HfO/sub 2/ remain low (EOT of 12.0 /spl Aring/. HfO/sub 2/ with 1/spl times/10/sup -3/ A/cm/sup 2/ at Vg=1.0 V). Reasonable N- and P-MOSFET characteristics such as subthreshold swing of 74 mV/decade and output currents were also demonstrated.

Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8 /spl Aring/-12 /spl Aring/)

MOSFETs with equivalent oxide thickness of 8-12 /spl Aring/ have been demonstrated by using high-K gate dielectric thin films (HfO/sub 2/) and TaN gate electrode. Both self-aligned (higher thermal budget process) and non-self-aligned process (low thermal budget as in the replacement gate process) were used and compared. Excellent electrical characteristics (e.g. S/spl sim/68 mV/dec) and reliability characteristics (e.g. high E/sub BD/, low charge trapping and SILC) were also obtained.

Single-layer thin HfO/sub 2/ gate dielectric with n+-polysilicon gate

MOSCAPs and MOSFETs of a single-layer thin HfO/sub 2/ gate dielectric with n+ polysilicon gate were fabricated and characterized. Polysilicon process was optimized such that leakage current and equivalent oxide thickness of HfO/sub 2/ remained low. Excellent C-V properties (e.g. low Dit and frequency dispersion) and reliability characteristics were obtained. Reasonable MOSFET quality was also demonstrated.

Effect of barrier layer on the electrical and reliability characteristics of high-k gate dielectric films

Electrical and reliability characteristics of several metal/high-k/(barrier layer)/Si capacitor structures have been investigated. The equivalent oxide thickness (EOT) increased as the annealing temperature increased, especially in oxygen ambient. Jet vapor-deposited (JVD) nitride was found to be a good oxidation barrier which is important for achieving thin EOT. Introducing TiO/sub 2/ as a barrier layer reduced the leakage current and EOT of Pt/BST/Si capacitor. The conduction mechanism in Pt/TiO/sub 2//Si structure was found to be tunneling-like behaviour limited by the interfacial layer. Hysteresis could be minimized by the optimization of the annealing process. In reliability characteristics, TiO/sub 2/ revealed no significant degradation and exhibited better wear-out properties than conventional SiO/sub 2/.

Transconductance improvement in surface-channel SiGe p-metal-oxide-silicon field-effect transistors using a ZrO2 gate dielectric

Silicon and surface-channel SiGe p-metal-oxide-silicon field-effect transistors (p-MOSFETs) using a ZrO2 gate dielectric with equivalent oxide thickness (EOT) less than 20 A was fabricated. These p-MOSFETs show similar behavior to that of other high-k gate dielectric p-MOSFETs reported in the literature, and mobility enhancement is observed in the surface-channel SiGe p-MOSFETs.

A 45 nm gate length high performance SOI transistor for 100 nm CMOS technology applications

In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, using a 16 /spl Aring/ nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 /spl mu/A//spl mu/m and 460 /spl mu/A//spl mu/m were achieved at 20 nA//spl mu/m for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA//spl mu/m. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.

High-K gate dielectrics

High-K dielectric thin films have been investigated as alternative gate dielectrics. Our results suggest that single-layer sputtered ZrO2 or HfO2 thin films deposited directly on Si substrate, without the use of a barrier layer, exhibit excellent electrical and reliability characteristics. Equivalent oxide thickness as thin as 9 angstrom with leakage current of about 10-2 A/cm2 was achieved. This is the lowest EOT value ever reported for ZrO2 and HfO2 thin films. Low charge- trapping, high breakdown field, and negligible stress- induced leakage currents have also been obtained.