Wen-Yi Chen

Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process

In high-voltage technologies, silicon-controlled rectifier (SCR) is usually embedded in output arrays to provide a robust and self-protected capability against electrostatic discharge (ESD). Although the embedded SCR has been proven as an excellent approach to increasing ESD robustness, mistriggering of the embedded SCR during normal circuit operating conditions can bring other application reliability concerns. In particular, the safe operating area (SOA) of output arrays due to SCR insertion has been seldom evaluated. In this paper, the impact of embedding SCR to the electrical SOA (eSOA) of an n-channel LDMOS (nLDMOS) array has been investigated in a 24-V bipolar CMOS-DMOS process. Experimental results showed that the nLDMOS array suffers substantial degradation on eSOA due to embedded SCR. Design approaches, including a new proposed poly-bending (PB) layout, were proposed and verified in this paper to widen the eSOA of the nLDMOS array with embedded SCR. Both the high ESD robustness and the improved SOA of circuit operation can be achieved by the new proposed PB layout in the nLDMOS array.

Interfacial layer dependence on device property of high-κ TiLaO Ge/Si N-type metal-oxide-semiconductor capacitors at small equivalent-oxide thickness

We have investigated the device property dependence of high dielectric-constant (high-κ) TiLaO epitaxial-Ge/Si n-type metal-oxide-semiconductor (n-MOS) capacitors on different GeO2 and SiO2 interfacial layers. Large capacitance density of 3.3 μF/cm2, small equivalent-oxide thickness (EOT) of 0.81 nm and small C-V hysteresis of 19 mV are obtained simultaneously for MOS capacitor using ultrathin SiO2 interfacial layer, while the device with ultrathin interfacial GeO2 shows inferior performance of larger 1.1 nm EOT and poor C-V hysteresis of 93 mV. From cross-sectional transmission electron microscopy, secondary ion mass spectroscopy, and x-ray photoelectron spectroscopy analysis, the degraded device performance using GeO2 interfacial layer is due to the severe Ge outdiffusion, thinned interfacial GeO2 and thicker gate dielectric after 550 °C rapid-thermal anneal.

Comparison of MONOS memory device integrity when using Hf1-x-yNxOy trapping layers with different N compositions

We have studied the nitrogen composition dependence of the characteristics of Hf_1-x-yN_xO_y/SiO₂/Si MONOS memory devices. By increasing the N composition in the Hf_1-x-yN_xO_y trapping layer, both the memory window and high-temperature retention improved. The Hf_0.3N_0.2O_0.5 MONOS device displayed good characteristics in terms of its plusmn9-V program/erase (P/E) voltage, 100-mus P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85degC or 1.5 V at 125degC.

New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS

In high-voltage applications, large-array n-channel lateral DMOS (LA-nLDMOS) is usually required to provide high driving capability. However, without following the foundry-suggested electrostatic discharge (ESD) design guidelines in order to reduce total layout area, LA-nLDMOS is easily damaged once the parasitic bipolar junction transistor is triggered under ESD stresses. Accordingly, the bipolar triggering of LA-nLDMOS usually limits the ESD robustness of LA-nLDMOS, particularly in the open-drain structure. In this letter, a new layout arrangement for LA-nLDMOS has been proposed to suppress the bipolar triggering under ESD stresses. Measurement results in a 0.5-¿m 16-V bipolar CMOS DMOS process have confirmed that the new proposed layout arrangement can successfully increase the human-body-model ESD level of the LA-nLDMOS with effective width of 3000 ¿m from the original 0.75 kV up to 2.75 kV.

Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

To avoid latch-up failure in high voltage integrated circuits, a source-side engineering technique for on-chip ESD protection nLDMOS is proposed in this work. Experimental results have been verified in a 0.5-µm 16-V bipolar CMOS DMOS technology. Measurement results from transmission-line-pulsing system show that the proposed source-side engineering method can effectively increase the holding voltage of the nLDMOS from 10.5V to 16.2V. Transient-induced latch-up tests show that the proposed source-side engineering technique significantly improves the latch-up immunity of nLDMOS in on-chip ESD protection circuit.

Comparison of MONOS Memory Device Integrity When Using Trapping Layers With Different N Compositions

We have studied the nitrogen composition dependence of the characteristics of Hf_1-x-yN_xO_y/SiO₂/Si MONOS memory devices. By increasing the N composition in the Hf_1-x-yN_xO_y trapping layer, both the memory window and high-temperature retention improved. The Hf_0.3N_0.2O_0.5 MONOS device displayed good characteristics in terms of its plusmn9-V program/erase (P/E) voltage, 100-mus P/E speed, large initial 2.8-V memory window, and a ten-year extrapolated retention of 1.8 V at 85degC or 1.5 V at 125degC.

Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits

Safe operating area (SOA) in power semiconductors is one of the most important factors affecting device reliability. The SOA region of power MOSFETs must be well characterized for using in circuit design to meet the specification of applications, particularly including the time domain of circuit operations. In this paper, the characterization of SOA in the time domain is performed with the experimental measurement on silicon devices, and the useful techniques to improve SOA of power MOSFETs for using in high-voltage integrated circuits are overviewed.

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

The n-channel lateral double-diffused metal-oxide- semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-¿m 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35- ¿m 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.

Investigation on the Validity of Holding Voltage in High-Voltage Devices Measured by Transmission-Line-Pulsing (TLP)

Latch-up is one of the most critical issues in high-voltage (HV) ICs due to the high power-supply voltages. Because the breakdown junction of an HV device is easily damaged by the huge power generated from a DC curve tracer, the device immunity against latch-up is often referred to the transmission-line-pulsing (TLP)-measured holding voltage. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25- 18-V bipolar CMOS DMOS process to evaluate the validity of latch-up susceptibility by referring to the holding voltage measured by 100- and 1000-ns TLP systems and curve tracer. Long-pulse TLP measurement reveals the self-heating effect and self-heating speed of the n-channel LDMOS. The self-heating effect results in the TLP system to overestimate the holding voltage of HV n-channel LDMOS. Transient latch-up test is further used to investigate the susceptibility of HV devices to latch-up issue in field applications. As a result, to judge the latch-up susceptibility of HV devices by holding voltage measured from TLP is insufficient.

Higher Gate Capacitance Ge n-MOSFETs Using Laser Annealing

By applying laser annealing (LA) on both gate dielectrics and source/drain activation, the TaN/ZrO₂/La₂O₃/SiO₂ on Ge n-MOSFETs shows a high gate capacitance density, a small n⁺/p-junction ideality factor of 1.10, a small subthreshold swing (SS) of 106 mV/dec, and a good high-field mobility of 285 or 340 cm²/V·s after gate leakage correction at 1 MV/cm, at a small 0.95-nm equivalent oxide thickness (EOT). To the best of our knowledge, this is the first demonstration of significantly high gate capacitance in MOSFETs by LA. This is also the highest 1-MV/cm mobility at the smallest EOT of Ge n-MOSFETs and better than the SiO₂/Si universal mobility.