Jiaotuo Ye

FEA study of the evolution of wafer warpage during reflow process in WLP

In this paper, the evolution of wafer warpage during reflow process in wafer level packaging (WLP) is investigated by finite element analysis (FEA). The investigation focuses on three different fan-in WLP technologies: ball on polymer WLP without under bump metallurgy (UBM), ball on polymer WLP with thick UBM layer and encapsulated copper post WLP. Both wafer-level model and ball-level model are built and the results indicate that wafer warpage derived from ball-level model is compatible with wafer-level model. Ball on polymer WLP with thick UBM layer has the maximum warpage after reflow process. Reflow profiles with different cooling rate are also simulated.

Experimental identification of warpage origination during the wafer level packaging process

Redistribution layer (RDL) composing of polyimide (PI) dielectric layer and electro-chemical deposited (ECD) Cu trace is a critical part for wafer level packaging (WLP). One concern of this multi-layered film structure is the wafer warpage induced during the process, which poses threats to automatic handling, 3-D integration and device reliability. In this paper, the warpage origination during the WLP process was identified and analyzed by experiments and simulations. The wafer warpage evolution during the WLP process was measured by a Multi-beam Optical Sensor system. We found that the cure shrinkage of PI has little effect on the warpage, however, it is mainly caused by the coefficient of thermal expansion (CTE) mismatch between the deposited materials. The ECD Cu trace in RDL accounted for a substantial proportion to the total wafer warpage and lead to a hysteresis response during the thermal processes indicating plastic deformation has taken place. For in-depth understanding, the plastic behavior of ECD Cu film was investigated and the kinematic hardening plastic model was established. Finally, the stresses distribution in RDL structure was simulated by numerical method and the influence of ECD Cu trace pattern on the wafer warpage was evaluated.

Wafer-Level Packaging Design With Through Substrate Grooves as Interconnection for GaAs-Based Image Sensor

A wafer-level packaging design for GaAs-based image sensor is presented. Key processes, such as GaAs/glass wafer bonding, GaAs substrate thinning, through substrate grooves (TSGs) fabrication, redistribution layer formation, polymer passivation, and laser jet bumping, are examined and characterized. GaAs image sensor package with 64 leads is successfully fabricated on 4-in thinned GaAs/glass test vehicle wafer. In the package, two long TSGs are wet etched as the interconnection path. Process parameters are systematically studied and given. Then, fabrication results of these processes were discussed. Finally, electrical tests show that ohmic contact is obtained with a resistance of around 30 Ω between two nearby interconnections.

System integration for miniature node of wireless sensor network (WSN)

A type of 3D-SiP (System in Package) package for wireless sensor network (WSN) node was designed and developed based on an embedded FR-4 substrate using 3D technology (including, embedded way and stacked way) and SiP technology. The 3D-SiP package including sensor (sound or vibration) module, baseband ASIC chips, digital signal processor (DSP) chips, other chips and various passive components, was studied. FCOB (flip-chip on board), COB (chip on board), BGA technologies, wire bonding flip-chip bonding and surface mount (SMT) etc. interconnection technologies were combined together. Several kinds of solder materials with different melting points were used for initial and final vertical interconnections for the sake of compatibility of all levels interconnections by reflowing. High density WSN node with ASIC chip embedded in and sensor module stacked on high density multi-layer FR-4 substrate was designed and manufactured. The thermal management was conducted and the thermal related reliability of 3D-SiP were simulated and evaluated respectively.

The novel assembly method of a field deployable biosensor unit

In this paper we report the novel assembly method of a biosensor unit based on 64 pixel photodetector array with a proprietary semiconductor quantum dots (QDs) quantum well (QW) hybrid structure. There is significantly lower dark current for optimized high sensitivity detector. The capacitive trans-impedance amplifier (CTIA)-correlated double sampling (CDS) readout circuit can readout weak optical signal which respond by photodetector. To minimize the packaging size of our biosensor unit, a double-sided printed circuit board designed to decrease noise by special package making photodetector array can operate at room temperature and lower temperature for get better performance. The readout circuit is bonding on the backside of substrate through silicon via (TSV) structure, and the photodetector array bonding on the front side of substrate for making the optic signal through to photosensitive window of detector. A highly integrated Cortex-M4 MCU (STM32F407) has build the data acquisition and analysis unit providing Wi-Fi interface to communicate with the PC software for biosensor unit rapid diagnosis infectious disease and more easy carry.

Adhesive wafer bonding of GaAs/Glass with Benzocyclobutene and dry film for GaAs CCD

This paper studies adhesive wafer bonding of 4 inches GaAs CCD device wafer with Optik glass for wafer level packaging. In this work, Benzocyclobutene (BCB) and dry film (DF) were proposed as the bonding material. Efforts were devoted to the warpage control. The relationship between the extent of warpage and bonding parameters, such as the bonding profile, the thickness of bonding material, supporting wafer, were studied. The total bonding area and bonding strength were also studied. Under the optimized bonding conditions, warpage of 90.40 um was obtained for BCB bonding. The optimized condition was demonstrated. Nearly 100% bonding area was obtained for BCB bonding. For DF bonding, the warpage was 123.47. The bonding strength was 15.89 MPa for DF bonding.

Warpage characteristics of wafer-level package of MEMS with glass frit bonding

Warpage is one of the challenging problems for wafer level package (WLP). Especially, the bonding process of multiple wafers will bring additional stress to WLP and warpage of WLP. This paper aims at the stress and warpage characteristics of the WLP (consisting of silicon cover wafer and silicon MEMS wafer) with glass frit bonding. The finite element (FE) method and MOS (Multi-beam Optical Sensor) technology were used. Simulation result indicated that WLP presents almost zero warpage. MOS measurement result indicated that WLP actually presents convex warpage instead of zero warpage. It turned out that the convex warpage results from the temperature difference between WLP wafers (i.e. cover wafer and MEMS wafers) in the course of post-bond cooling. Taken the temperature difference into account, the simulation result was consistent with experiment results. Furthermore, on the basis of the convex warpage value the stress of WLP was also calculated so as to understand the stress distribution and estimate the reliability level of the MEMS device.

Analysis of thermal stresses in redistribution layer of WLP with different arrangement of interconnections

Thick polyimide film and electroplated Cu lines are widely adopted in redistribution layer of wafer level packaging. One potential reliability problem is the stresses generated in the thermal process. In this paper, the evolution of thermal stresses and plastic strain in two-level interconnections in redistribution layer of WLP was analyzed by recourse to the finite element analysis and Taguchi method. Cu lines embedded in polyimide with different aspect ratio, aligned vertically or arranged in a staggered manner were considered. Attention was devoted to the thermal stresses and plastic strain evolution and their dependency on the geometry structure. The constitutive response of Cu was taken to be elastic-plastic, with the post-yield behavior following the kinematic hardening model. The stresses and plastic strain are found to be a little higher in the low-level lines, for both aligned and staggered arrangements. A larger aspect ratio is helpful to reduce the stress, but it will generate large plastic deformation. The aspect ratio also plays a key role in wafer curvature and large aspect ratio will decrease the curvature.

Warpage and stress optimization of wafer-level package of MEMS with glass frit bonding

Warpage issue of wafer level package (WLP) has caught the attention of WLP industry. This paper aims at the warpage characteristics and optimization of the WLP (consisting of silicon MEMS wafer and silicon cover wafer) with glass frit bonding. Finite-element method (FEM) was used to study the warpage and stress optimization of the Si-Si bonding WLP. Some factors which affect WLP warpage, such as CTE (coefficient of thermal expansion) and Youngs modulus of glass frit, ring thickness & width of glass frit and bonding temperature etc. were optimized. The stress of WLP was also calculated and the reliability level of the MEMS device was estimated. It turned out that CTE and Young modulus of glass frit are the key parameters for decreasing WLP warpage and stress and promoting the MEMS WLP. Ring width of glass frit and the thickness of silicon cover plate wafer have little impacts on WLP stress and warpage. With the optimized parameters taken into account, the stress in MEMS WLP falls down. Those optimization results have been put into actual WLP manufacture.

A new designed trench structure to reduce the wafer warpage in wafer level packaging process

Wafer warpage in wafer level packaging process poses threats to wafer handling, process qualities, and can also lead to unacceptable reliability problems. With larger diameter wafer adopted, this issue becomes more serious. In the paper, a new designed trench structure was introduced in WLP process to reduce the final wafer warpage. Both experiment and simulation methods are used to investigated the effect of the trenches on the wafer warpage. The result indicates that, by forming deep trenches, the stress of individual dies is decoupled and the total the wafer warpage will be decreased. The effect of the geometry of these trenches on the mechanical behavior of the wafer was further studied by simulation.