Chunsheng Zhu

FEA study of the evolution of wafer warpage during reflow process in WLP

In this paper, the evolution of wafer warpage during reflow process in wafer level packaging (WLP) is investigated by finite element analysis (FEA). The investigation focuses on three different fan-in WLP technologies: ball on polymer WLP without under bump metallurgy (UBM), ball on polymer WLP with thick UBM layer and encapsulated copper post WLP. Both wafer-level model and ball-level model are built and the results indicate that wafer warpage derived from ball-level model is compatible with wafer-level model. Ball on polymer WLP with thick UBM layer has the maximum warpage after reflow process. Reflow profiles with different cooling rate are also simulated.

Experimental identification of warpage origination during the wafer level packaging process

Redistribution layer (RDL) composing of polyimide (PI) dielectric layer and electro-chemical deposited (ECD) Cu trace is a critical part for wafer level packaging (WLP). One concern of this multi-layered film structure is the wafer warpage induced during the process, which poses threats to automatic handling, 3-D integration and device reliability. In this paper, the warpage origination during the WLP process was identified and analyzed by experiments and simulations. The wafer warpage evolution during the WLP process was measured by a Multi-beam Optical Sensor system. We found that the cure shrinkage of PI has little effect on the warpage, however, it is mainly caused by the coefficient of thermal expansion (CTE) mismatch between the deposited materials. The ECD Cu trace in RDL accounted for a substantial proportion to the total wafer warpage and lead to a hysteresis response during the thermal processes indicating plastic deformation has taken place. For in-depth understanding, the plastic behavior of ECD Cu film was investigated and the kinematic hardening plastic model was established. Finally, the stresses distribution in RDL structure was simulated by numerical method and the influence of ECD Cu trace pattern on the wafer warpage was evaluated.

Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature (Tg) of polyimide will help to reduce the final wafer warpage.

System integration for miniature node of wireless sensor network (WSN)

A type of 3D-SiP (System in Package) package for wireless sensor network (WSN) node was designed and developed based on an embedded FR-4 substrate using 3D technology (including, embedded way and stacked way) and SiP technology. The 3D-SiP package including sensor (sound or vibration) module, baseband ASIC chips, digital signal processor (DSP) chips, other chips and various passive components, was studied. FCOB (flip-chip on board), COB (chip on board), BGA technologies, wire bonding flip-chip bonding and surface mount (SMT) etc. interconnection technologies were combined together. Several kinds of solder materials with different melting points were used for initial and final vertical interconnections for the sake of compatibility of all levels interconnections by reflowing. High density WSN node with ASIC chip embedded in and sensor module stacked on high density multi-layer FR-4 substrate was designed and manufactured. The thermal management was conducted and the thermal related reliability of 3D-SiP were simulated and evaluated respectively.

Experimental identification of thermal induced warpage in polymer-metal composite films

Abstract Composite thick films consisting of multi-layered polymers and metals are widely used in integrated circuits(IC) and its packaging, and it arises intricate stress and warpage problems due to complex inner stress distribution and evolution. The wafer warpage origination and evolution of multi-layered polyimide (PI)/Cu composite film is measured in-situ by a Multi-beam Laser Optical Sensor (MOS) system. Its found that PI has an intricate influence on wafer warpage evolution and Cu plastic deformation due to viscoelasticity and glass-transition, and the influence differs in different structures and at different temperatures. Nonlinearity of the curvature–temperature curve of the composite occurs at much lower temperature than in single PI or Cu film, showing mutual effect of PI and Cu. Unlike bare or capping PI film that totally stress relaxed at high temperature, bottom PI coated by Cu film sustains a medium compressive stress, indicating that Cu coating film has restrained stress relaxation of PI. The warpage evolution during heating is different from that during cooling, perhaps due to different deformation mechanism.

Thermomechanical behavior of nanotwinned copper interconnection line in wafer level packaging and the influence on wafer warpage

Nanotwinned copper is a promising material to overcome the difficulties in wafer level packaging when interconnection stripe shrinks to typical grain size for its excellent thermal and mechanical properties. In this work, a novel wafer level interconnection, with the width of around 10 micrometers and grains tailored by textural nanotwinned copper, was prepared by pulse electrodeposition. The twin lamellae thickness was in the range of 20-50nm. Different from typical reported recrystallization model in nanotwins formation, a layer-by-layer growth was observed and a corresponding terrace model was proposed in current work. The crystallographic texture was proofed to be basically thermal stable after annealed at 300°C. Compared with normal copper thick film, the nanotwinned grain structure was observed quite stable with less morphological evolution demonstrated by in situ wafer warpage detection, showing improved thermal stability of the interconnection. This new interconnection can be potentially used to reduce thermal induced wafer warpage in wafer level packaging.

Warpage characteristics of wafer-level package of MEMS with glass frit bonding

Warpage is one of the challenging problems for wafer level package (WLP). Especially, the bonding process of multiple wafers will bring additional stress to WLP and warpage of WLP. This paper aims at the stress and warpage characteristics of the WLP (consisting of silicon cover wafer and silicon MEMS wafer) with glass frit bonding. The finite element (FE) method and MOS (Multi-beam Optical Sensor) technology were used. Simulation result indicated that WLP presents almost zero warpage. MOS measurement result indicated that WLP actually presents convex warpage instead of zero warpage. It turned out that the convex warpage results from the temperature difference between WLP wafers (i.e. cover wafer and MEMS wafers) in the course of post-bond cooling. Taken the temperature difference into account, the simulation result was consistent with experiment results. Furthermore, on the basis of the convex warpage value the stress of WLP was also calculated so as to understand the stress distribution and estimate the reliability level of the MEMS device.

Analysis of thermal stresses in redistribution layer of WLP with different arrangement of interconnections

Thick polyimide film and electroplated Cu lines are widely adopted in redistribution layer of wafer level packaging. One potential reliability problem is the stresses generated in the thermal process. In this paper, the evolution of thermal stresses and plastic strain in two-level interconnections in redistribution layer of WLP was analyzed by recourse to the finite element analysis and Taguchi method. Cu lines embedded in polyimide with different aspect ratio, aligned vertically or arranged in a staggered manner were considered. Attention was devoted to the thermal stresses and plastic strain evolution and their dependency on the geometry structure. The constitutive response of Cu was taken to be elastic-plastic, with the post-yield behavior following the kinematic hardening model. The stresses and plastic strain are found to be a little higher in the low-level lines, for both aligned and staggered arrangements. A larger aspect ratio is helpful to reduce the stress, but it will generate large plastic deformation. The aspect ratio also plays a key role in wafer curvature and large aspect ratio will decrease the curvature.

Warpage and stress optimization of wafer-level package of MEMS with glass frit bonding

Warpage issue of wafer level package (WLP) has caught the attention of WLP industry. This paper aims at the warpage characteristics and optimization of the WLP (consisting of silicon MEMS wafer and silicon cover wafer) with glass frit bonding. Finite-element method (FEM) was used to study the warpage and stress optimization of the Si-Si bonding WLP. Some factors which affect WLP warpage, such as CTE (coefficient of thermal expansion) and Youngs modulus of glass frit, ring thickness & width of glass frit and bonding temperature etc. were optimized. The stress of WLP was also calculated and the reliability level of the MEMS device was estimated. It turned out that CTE and Young modulus of glass frit are the key parameters for decreasing WLP warpage and stress and promoting the MEMS WLP. Ring width of glass frit and the thickness of silicon cover plate wafer have little impacts on WLP stress and warpage. With the optimized parameters taken into account, the stress in MEMS WLP falls down. Those optimization results have been put into actual WLP manufacture.

A new designed trench structure to reduce the wafer warpage in wafer level packaging process

Wafer warpage in wafer level packaging process poses threats to wafer handling, process qualities, and can also lead to unacceptable reliability problems. With larger diameter wafer adopted, this issue becomes more serious. In the paper, a new designed trench structure was introduced in WLP process to reduce the final wafer warpage. Both experiment and simulation methods are used to investigated the effect of the trenches on the wafer warpage. The result indicates that, by forming deep trenches, the stress of individual dies is decoupled and the total the wafer warpage will be decreased. The effect of the geometry of these trenches on the mechanical behavior of the wafer was further studied by simulation.