Wes E. Baca

Planar quantum transistor based on 2D–2D tunneling in double quantum well heterostructures

We report on our work on the double electron layer tunneling transistor (DELTT), based on the gate-control of two-dimensional -- two-dimensional (2D-2D) tunneling in a double quantum well heterostructure. While previous quantum transistors have typically required tiny laterally-defined features, by contrast the DELTT is entirely planar and can be reliably fabricated in large numbers. We use a novel epoxy-bond-and-stop-etch (EBASE) flip-chip process, whereby submicron gating on opposite sides of semiconductor epitaxial layers as thin as 0.24 microns can be achieved. Because both electron layers in the DELTT are 2D, the resonant tunneling features are unusually sharp, and can be easily modulated with one or more surface gates. We demonstrate DELTTs with peak-to-valley ratios in the source-drain I-V curve of order 20:1 below 1 K. Both the height and position of the resonant current peak can be controlled by gate voltage over a wide range. DELTTs with larger subband energy offsets ({approximately} 21 meV) exhibit characteristics that are nearly as good at 77 K, in good agreement with our theoretical calculations. Using these devices, we also demonstrate bistable memories operating at 77 K. Finally, we briefly discuss the prospects for room temperature operation, increases in gain, and high-speed.

Double electron layer tunnelling transistor (DELTT)

We demonstrate the double electron layer tunnelling transistor (DELTT), based on the gate control of two-dimensional-two-dimensional tunnelling in a double quantum well. Unlike previously proposed resonant tunnelling transistors, the DELTT is entirely planar and can be easily fabricated in large numbers. At 1.5 K we demonstrate peak-to-background ratios of :1 in source-drain conductance versus gate voltage and peak-to-valley ratios of :1 in the source-drain current versus source-drain voltage. Using a single DELTT in series with a load resistor, we demonstrate low-power bistable memories at 1.5 K. We also demonstrate a unipolar complementary static RAM by connecting two DELTTs in series.

Dual-side electron beam lithography for independent submicron gating of double quantum well devices

We describe the first demonstration of dual-side electron beam lithography in achieving independent submicron gating in double quantum well devices. The technique utilizes the epoxy-bond and stop-etch process to remove the substrate material which allows the backside gates to be placed in close proximity (less than 1 m) to the frontside gates. The use of electron beam lithography allows both the definition of submicron features and the precise alignment of the front and back features to each other. We have applied this technique to the fabrication of double quantum point contacts on coupled AlGaAs/GaAs double quantum wells. Low-temperature transport measurements clearly show the formation of coupled, independently controllable mesoscopic structures in each of the two quantum wells.