William Cheng-Yu Ma

Asymmetric Driving Current Modification of CMOS LTPS-TFTs With

In this paper, the asymmetric driving current Idrv modification of CMOS low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO₂ gate dielectric is demonstrated by the interfacial layer (IL) engineering of HfO₂/poly-Si interface. P-channel LTPS-TFT has much higher Idrv ~ 0.789 mA than the n-channel LTPS-TFT ~ 0.274 mA under the same overdrive gate voltage. This asymmetric I_drv is due to the characteristics of field effect mobility μ_FE that p-channel LTPS-TFT has much higher hole μ_FE ~ 80.16 cm²/Vs than the electron μ_FE ~ 38.26 cm²/V s of n-channel LTPS-TFT. The modification of HfO₂/poly-Si interface by O₂ plasma can enhance the electron μFE ~ 34% and reduce the hole μ_FE ~ 22.4%, resulting in balanced I_drv of CMOS LTPS-TFTs that n-channel device shows I_drv ~ 0.553 mA and p-channel device shows I_drv ~ 0.590 mA. In addition, the phonon scattering would also be improved by the IL growth and recovered to initial condition after IL removal. Consequently, the IL engineering of CMOS LTPS-TFTs with HfO₂ gate dielectric would be a good candidate for the application of system-on-panel or 3-D integrated circuits.

{\rm HfO}_{2}

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states (N_it) near the conduction band edge. The ON-state current (I_ON) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N₂ plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N_it obviously, which greatly enhances the surface potential modulation by the gate and improves the I_ON value of poly-Si TFETs ~3.7×. The OFF-state current (I_min) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of ~40%, because of the passivation of grain boundary trap (N_trap) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42 × 10⁵ to 6.13 × 10⁶. In addition, the subthreshold swing, I_ON, and I_min of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device.

Gate Dielectric

In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (Nit) and bulk traps (NGB). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit ~4.5× higher ON-state current ION, subthreshold swing reduction ΔS.S. ~202 mV/decade, and larger ~7.2× ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced Nit ~ 0.60× and a reduced NGB ~ 0.36×, respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics.

Performance Improvement of Poly-Si Tunnel FETs by Trap Density Reduction

In this paper, NH3 plasma directly applied to the surface of poly-Si channel is studied for the development of high-performance low-temperature polycrystalline-silicon thinfilm transistors (LTPS-TFTs) with HfO2 high-κ gate dielectric. The reduction of threshold voltage from 1.52 to 0.62 V, the decrease of subthreshold swing from 227 to 151 mV/decade, and the enhancement of field effect mobility μFE from 31 to 65 cm2/V s are observed after NH3 plasma surface treatment. It can be attributed to the NH3 plasma surface treatment enabling defect passivation and plasma-induced interfacial layer (PIL) growth. To decouple the impacts of defect passivation and PIL growth, the device without PIL is also fabricated. This paper demonstrates the important impacts of NH3 plasma surface treatment on the improvement of electrical characteristics of LTPS-TFTs.

Impact of Crystallization Method on Poly-Si Tunnel FETs

In this paper, an ultra-thin-body thin-film transistor (UTB-TFT) with a raised source/drain structure is demonstrated and compared with a conventional thin-film transistor. A significant suppression of leakage current and an improvement in subthreshold swing (SS) resulting from the reduced body thickness is observed. The minimum current can be decreased from 245 pA to 42 pA as the channel film thickness is scaled down from 60 nm to 10 nm. However, an ultra-thin-channel film constrains the average grain size and severely impacts the saturation current. Fortunately, by decreasing the gate oxide thickness from 20 nm to 10 nm, the saturation current of a UTB-TFT can be significantly increased from 13 μA to 25 μA. Experimental results suggest that UTB-TFTs with a sub-10 nm gate oxide display great promise for future low-power, high-performance three-dimensional integrated circuits.

Threshold Voltage Reduction and Mobility Improvement of LTPS-TFTs With NH 3 Plasma Treatment

In this paper, the opposite impacts of N₂O plasma surface treatment on the n- and p-channel low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO₂ gate dielectric are investigated. Significant performance improvement of n-channel LTPS-TFT by N₂O plasma surface treatment is observed, including threshold voltage reduction ΔV_TH ~ -0.57 V, 1.55× higher transconductance G_m, and 1.82× higher driving current I_drv. However, p-channel LTPS-TFT shows serious performance degradation after N₂O plasma surface treatment, including threshold voltage increase ΔV_TH ~ -0.99 V, transconductance G_m reduction, and driving current I_drv degradation. The difference of the two mechanisms of N₂O plasma surface treatment, namely, plasma induced interfacial layer (PIL) growth effect and trap passivation effect on poly-Si, is elaborated by a process of the PIL removal after the PIL growth. As a result, the trap passivation effect benefits both n- and p-channel LTPS-TFTs. The PIL growth effect shows the opposite impacts on the n- and p-channel LTPS-TFTs, that benefits n-channel LTPS-TFT and degrades p-channel LTPS-TFT seriously. Therefore, the negative impacts of N₂O plasma surface treatment on the p-channel LTPS-TFTs can be eliminated by a PIL removal step in the process. These results would be critical for the applications of system-on-panel and 3-D integrated circuit.

High-performance poly-Si TFT with ultra-thin channel film and gate oxide for low-power application

In this paper, tunnel field-effect transistor (TFETs) with polycrystalline-silicon (poly-Si) channel film has been demonstrated to exhibit better short-channel effects (SCEs) immunity than conventional poly-Si thin-film transistors. Oxygen (O2) plasma surface treatment before the deposition of gate dielectric can produce a plasma-induced interfacial layer, which can passivate the interface trap state density ~25%. In addition, the ON-state transconductance Gm is improved ~54% due to the decrease of tunneling distance of band-toband tunneling. However, the Gm improvement of poly-Si TFETs is decreased with the scaling down of channel length due to the less trap state density in the small area of poly-Si channel film. Moreover, the O2 plasma surface treatment can also reduce the grain boundary trap state density of poly-Si channel film ~37%, which can reduce the trap-assisted tunneling current of poly-Si TFETs to suppress the length dependence of drain leakage current in the subthreshold region. Consequently, the O2 plasma surface treatment can not only improve the ON-state current and OFF-state leakage current of poly-Si TFETs, but also further improve the SCEs of poly-Si TFETs.

Reverse Electrical Behavior of N-Channel and P-Channel LTPS-TFTs by N 2 O Plasma Surface Treatment

In this paper, positive-bias temperature instability (PBTI) stress with different stress voltage at T = 125 °C is executed on the high-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with HfO₂ gate dielectric and ammonia (NH₃) plasma surface treatment. The NH₃ plasma surface treatment on the poly-Si TFT with HfO₂ gate dielectric can significantly decrease the threshold voltage (V_TH) approximately -1.86 V, reduce the subthreshold slope (S.S.) approximately -88 mV/decade, enhance the transconductance (G_m) approximately 2.4×, and driving current (I_drv) approximately 2.34. In addition, the device degradation after PBTI stress with stress voltage V_G - V_TH = 7 V for 1000 s at T = 125 °C can also be improved after the NH₃ plasma surface treatment, such as the suppressing of VTH shift from 2.063 to 0.617 V, S.S. degradation quantity from 0.284 V/decade to 0.172 V/decade, and I_drv reduction from -77% to -44%. The improvement of the PBTI of poly-Si TFTs with NH₃ plasma surface treatment is attributed to the suppression of oxide charge trapping effect and the degradation of interface state density (N_it) and grain boundary trap state density (N_GB).