Yi-Hsuan Chen

Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7×12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing ~99 mV/dec, and high ION/IOFF >; 107 (VD = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC

It is known that metal-induced lateral crystallization (MILC) thin-film transistors (TFTs) exhibit higher on-state current, steeper subthreshold slope, and lower minimum leakage than solid-phase-crystallization TFTs. In this letter, we propose a tunneling TFT (T-TFT) fabricated by MILC method for the first time. The MILC T-TFTs demonstrate a lower subthreshold swing, ~ 232 mV/decade, than the other T-TFTs and a high ON/OFF ratio at VDS=1 V without any hydrogen-related plasma treatment. These improvements can be due to the reduction of defects at grain boundaries and the channel direction parallel to grains. The polycrystalline silicon T-TFTs fabricated in this letter show a great promise for low standby power circuits, drivers of active-matrix liquid crystal displays, and 3-D integrated circuits applications in the future.

Performance Improvement of Poly-Si Tunnel FETs by Trap Density Reduction

In this brief, the tunnel FETs (TFETs) with a polycrystalline-Si (poly-Si) channel have been demonstrated, and the performance of the poly-Si TFET shows a significant improvement by the reduction of interface trap states (N_it) near the conduction band edge. The ON-state current (I_ON) conduction mechanism, band-to-band tunneling, of poly-Si TFETs is strongly affected by the band bending of poly-Si channel. The N₂ plasma surface treatment before the gate dielectric deposition can produce a plasma-induced interfacial layer to reduce N_it obviously, which greatly enhances the surface potential modulation by the gate and improves the I_ON value of poly-Si TFETs ~3.7×. The OFF-state current (I_min) attributed to the trap-assisted tunneling (TAT) can also be reduced by a factor of ~40%, because of the passivation of grain boundary trap (N_trap) of the poly-Si channel film. Consequently, the ON/OFF current ratio is enhanced from 9.42 × 10⁵ to 6.13 × 10⁶. In addition, the subthreshold swing, I_ON, and I_min of poly-Si TFET exhibit superior short-channel effect immunity, which shows good feasibility for implementing high packing density of poly-Si thin-film transistors, such as 3-D nonvolatile memory and pixel driving device.

Impact of Crystallization Method on Poly-Si Tunnel FETs

In this letter, the impact of crystallization method on the electrical characteristics of polycrystalline silicon (poly-Si) tunnel field-effect transistors (TFETs) is investigated. Different crystallization methods may result in different amounts of interface traps (Nit) and bulk traps (NGB). TFETs crystallized with solid-phase crystallization (SPC) and metal-induced lateral crystallization (MILC) were fabricated and compared. In comparison with the SPC TFETs, the MILC TFETs exhibit ~4.5× higher ON-state current ION, subthreshold swing reduction ΔS.S. ~202 mV/decade, and larger ~7.2× ON/OFF current ratio. According to the measurement of a monitor poly-Si thin-film transistor, replacing SPC with MILC results in a reduced Nit ~ 0.60× and a reduced NGB ~ 0.36×, respectively. It can enhance the gate-to-tunnel junction controllability. Consequently, lowering trap density favors reducing power consumption of TFETs and provides a promising solution for future low-power driving circuits in portable electronics.

Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures

This paper reports the impacts of NH3 plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. off-state currents may be improved by increasing the oxide overetching depth. The on/ off current ratio may be also improved by increasing the oxide overetching depth. The NH3 plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH3 plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (<; 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. off-state currents can be improved by increasing Lmask, even when the oxide overetching depth and the gate oxide thickness are changed.

Novel Symmetric Vertical-Channel Ni-Salicided Poly-Si Thin-Film Transistors With High on/off-Current Ratio

We have successfully fabricated the symmetric vertical-channel Ni-salicided polycrystalline silicon thin-film transistors (VSA-TFTs) for the first time. The transfer characteristics of VSA-TFTs show a sharp turning between subthreshold and on state. The off -state currents can be improved by a modified overetching of oxide, equivalent dual-gate structure, and n⁺ floating-region length. The on-state currents can be enhanced by Ni-salicidation. The VSA-TFTs display a good subthreshold swing of 220 mV/dec, steep mobility increase (field-effect mobility of 76 cm²/V·s), and large on/off-current ratio of more than 10⁹ (<i>I</i>_OFF = 4 × 10^-14, <i>I</i>_ON = 7 × 10^-5, and <i>W</i>_mask/<i>L</i>_mask = 10 μm/3 μm).

High-performance poly-Si TFT with ultra-thin channel film and gate oxide for low-power application

In this paper, an ultra-thin-body thin-film transistor (UTB-TFT) with a raised source/drain structure is demonstrated and compared with a conventional thin-film transistor. A significant suppression of leakage current and an improvement in subthreshold swing (SS) resulting from the reduced body thickness is observed. The minimum current can be decreased from 245 pA to 42 pA as the channel film thickness is scaled down from 60 nm to 10 nm. However, an ultra-thin-channel film constrains the average grain size and severely impacts the saturation current. Fortunately, by decreasing the gate oxide thickness from 20 nm to 10 nm, the saturation current of a UTB-TFT can be significantly increased from 13 μA to 25 μA. Experimental results suggest that UTB-TFTs with a sub-10 nm gate oxide display great promise for future low-power, high-performance three-dimensional integrated circuits.

Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors

In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n+ region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n+ region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n+ region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n+ region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of VG is less than half of VD.

High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.) ~ 110 mV/dec., an extremely small drain induced barrier lowing (DIBL) ~12.2 mV V−1, and a high on/off ratio ~107 (V D = 1 V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.

Enhanced Subthreshold Slope and On-state Current in Tunneling Thin-Film-Transistors Using Metal Induced Lateral Crystallization

In this study, we propose a tunneling TFT fabricated by MILC method for the first time. The MILC tunneling TFTs demonstrate a lower subthreshold swing, ~232 mV/dec, than the other tunneling TFTs (T-TFTs) and a high on/off ratio > 10 6 at VDS=1V without any hydrogen related plasma treatment.