William D. Washkurak

High-speed, low-noise, fine-resolution TDI CCD imagers

It is well demonstrated that the CCD TDI mode of operation provides increased photosensitivity, relative to a linear CCD array, without the sacrifice of spatial resolution. However, in order to utilize the advantages which the TDI mode of operation offers, attention should be given to the CCD TDI design and tradeoffs which exist between the pixel pitch, dead space between pixels in the horizontal direction, high speed, high photosensitivity, high spatial resolution and wide dynamic range. For example, a 2000 pixel ThI with an MTF of 0.5 will have an effective spatial resolution of only 1000 pixels. Other tradeoffs also are present, such as high speed versus power dissipation which exist both in the array and in the on-chip output video amplifier. Further, noise considerations exist at the video on-chip output amplifier. These include high speed which demands high bandwidth, Johnson noise, 1/f noise, reset noise, and output signal charge to voltage sensitivity. In this paper we shall describe the novel approach which we used in the design of a 2048 x 96 TDI CCD imager. We shall show how we addressed successfully these design tradeoffs and issues. Details about the analysis and design of a high speed on-chip output amplifier will also be presented. In addition, we shall explain how the use of buried channel MOSFETs enabled us to address and solve the power dissipation, speed, and noise issues.

26.2-million-pixel CCD image sensor

A 26.2 million pixel CCD Imager Sensor has been successfully designed and fabricated. The device uses a full frame architecture with 5,120 X 5,120 pixels organization. With a pitch of 12 microns in both dimensions, the overall image zone is 61.44 mm X 61.44 mm. The charge storage capacity of each photosite is greater than 130,000 electrons and the minimum detectable charge is 50 electrons when correlated double sampling is used. The device is also capable of reduced dark current operation of 60 pA/cm2 when operated in the surface inversion mode. The device has four outputs, each of which can operate up to 12 MHz.

High-speed dual-output-channel stage-selectable TDI CCD image sensor for high-resolution applications

TDI sensors are a proven means of increasing the responsivity in a line scan imaging application. This paper describes the development of a family of high speed 96 stage TDI sensors. The sensor is available in a high resolution 2048 element version. A 512 element part will also be made. The number of TDI stages in the sensor can be selected in blocks of 6, 12, 24, 48, and 96 stages thus providing optimum sensitivity and performance over a wide range of illumination conditions. The device is fabricated using double metal, triple poly, buried channel, NMOS CCD process. The imaging region is 4-phase, 2-poly for maximum charge storage and optimum MTF. The pixel pitch on the sensor is 13 micrometers . The sensor employs a dual channel, 2-phase, 2-poly output shift register for high speed read-out. This technique enables halving the driving clock frequency thus reducing the power consumption which can be a severe problem at large data rates. Another benefit of dual channels is that each horizontal CCD (HCCD) pixel corresponds to two vertical CCD (VCCD) registers. As a result the charge storage capacity of the HCCD is doubled without having to increase the register width. The developed sensor operates at a combined data rate of up to 40 MHz. The maximum line speeds are 32,000 and 14,000 lines/sec for the 512 and 2048 element parts respectively. Methods to reduce the fixed pattern noise resulting from transfer inefficiencies between the two HCCD channels have been implemented.

Megapixel image sensors with forward motion compensation for aerial reconnaissance applications

Focal planes constructed of high speed, high resolution CCD image sensors are suitable for airborne reconnaissance applications, but have mainly consisted of linear and TDI array configurations. Until recently large format area arrays have been limited to staring applications, characterized by long integration times and slow readout rates. Large area reconnaissance focal planes require opto-mechanical systems for motion compensation across the imaging plane. A unique CCD architecture has been developed to provide electronic image motion compensation using variable speed vertical clocking segments. This architecture has been applied to very large full frame CCD sensors having 2048 X 2048 and 5040 X 5040 pixel formats.

A High Speed, Wide Dynamic Range Linear Dynasensor CCD Detector Array For Acousto-Optic Applications

Acousto-optic signal processing systems require linear detectors arrays with wide dynamic range and fast transient response. In the past, these two characteristics have not successfully been combined into a single integrated detector array with a large number of elements. DALSAs DYNASENSOR detector utilizes an optimized, ion implant doped, profiled MOSFET photodetector specifically designed for wide dynamic range. This detector, originally introduced by DALSA over a year ago, has been redesigned to improve transient response. The new device offers high speed, linear response characteristics at low light levels or short integration times (on the order of 1 microsecond). To achieve the short integration times necessary in acousto-optic applications, the DYNASENSOR has been implemented in a tapped array architecture with eight outputs and 256 photoelements. Operation of each output at 20 MHz yields detector integration times of 1.6 micro-seconds.

Design and electro-optical characterization of a 1024 x 1024 imager

Large format charge coupled device area arrays (1 million pixels or more) have proven to be useful in scientific, medical and industrial imaging applications. DALSA has developed a 1024 X 1024 pixel single output, full-frame area array incorporating 3-poly 3-phase buried channel NMOS CCD shift registers and a 10 micrometers X 10 micrometers pixel pitch. The device was fabricated with an additional buried channel implant (notch) in the pixel columns to increase charge storage capacity. In this paper the authors discuss the design and initial performance evaluation of the device. Preliminary measurements of the pixel charge storage capacity indicate 70,000 e- without notch and 140,000 e- with notch. The results indicate that the sensor should be suitable for a variety of applications such as high resolution machine vision, still photography, and scientific imaging.

Development of a 4-million-pixel CCD imager for aerial reconnaissance

High speed, high resolution CCD image sensors are suitable for airborne reconnaissance applications, but have mainly consisted of linear and TDI arrays. To date large format area arrays have been limited to staring applications, characterized by long integration times and slow readout rates. The authors have developed a 2048 (H) by 2048 (V) pixel, fast framing CCD array for aerial reconnaissance. The array incorporates high speed design features to provide operation in excess of 10 frames per second. Process modifications have been used in the design of a high signal capacity photoelement. A 12 micron square pixel pitch results in a relatively small focal plane diagonal of 34 millimeters. In this paper, we present the design and detailed performance evaluation of the array.

Surface channel clocked antiblooming technique for area-array CCD image sensors

Implementation ofover-illumination protection on area array image sensors has typically involved significant modifications to device design and/or processing. These modifications have caused degradation of device performance for example lateral antiblooming reduces fill factor and vertical antiblooming reduces near infra-red (NIR) quantum efficiency (QE). Clocked antiblooming is a technique that does not require any processing or design changes and does not degrade fill factor or MR QE. The technique involves clocking the imaging phases into and out of inversion during the integration time and relying on the surface recombination of electrons and holes to eliminate excess signal charge. The technique described in this paper allows clocked antiblooming with surface channel operation thus permitting large full well packets with small pixel geometries. Although surface channel operation is less efficient in terms of charge transfer efficiency there are some applications where maximum full well charge storage capability is important. 1.

256(V) x 256(H) full-frame area-array image sensor with on-chip electronics

- A 256 x 256 pixel full frame CCDimage sensor has been developed that incorporates on-chip d. c. bias generation and clocking. Using a small pixel pitch of 10 im (V) by 10 im (H) these features allow the array to be packaged into very small dimensions with a total pin count of seven pins. By virtue of the three phase architecture the full well storage capacity can be increased with surface channel operation maximizing resolution under conditions of low scene contrast. In addition a modified technique of surface recombination is used to provide blooming suppression. Together these features make it well suited for applications which require a high performance miniature sensor. I.

A 6032 x 32 time-delay and integration abuttable image sensor for use in airborne reconnaissance applications

Time-Delay and Integration (TDI) CCD sensors have been proven to increase the effective sensitivity in imaging applications where the image is scanned across the focal plane. This paper describes the development of a 6032 element, 32-stage TDI imager for airborne reconnaissance applications. The device is fabricated using a 3-poly 3-phase NMOS process, incorporating buried channel CCDs throughout. It is one-side buttable to produce an array of over 12,000 contiguous elements and is capable of read rates of over 4000 lines per second. For fast readout, the design incorporates dual horizontal CCDs for a total of four outputs in the abutted configuration. The architecture also allows dynamic selection in the number of TDI stages.