William G. Oldham

Copper Transport in Thermal SiO2

The transport of copper in silicon dioxide thermally grown on single crystalline silicon was studied by capacitance techniques, secondary ion mass spectroscopy (SIMS) analysis, and Rutherford backscattering spectrometry (RBS). Metal/oxide/silicon (MOS) capacitors were used to study the penetration of copper into the oxide as a function of temperature and applied electric field. The role of a titanium layer between the copper and the oxide was also studied. Bias-thermal stress (BTS) studies of MOS structures were conducted at 150 o C to 300 o C with an electric field of 1 MV/cm for times ranging between 10 min and 168 h

A general simulator for VLSI lithography and etching processes: Part I—Application to projection lithography

A simulator is described which produces line-edge profiles at various key stages in integrated circuit processing. Optical models are included for contact and projection lithography. The effects of multiple wavelengths, defocus, and partially coherent sources may be simulated in projection lithography. The positive resist model of Dill is used with the string development model of Jewett to obtain resist line-edge profiles. The string model is generalized to surface reaction rate limited etching of any layer. The application of the simulator to projection lithography is illustrated with a number of examples including monochromatic and multiwavelength exposure, the effect of a post-exposure anneal, plasma descum, and defocus.

Interface states in abrupt semiconductor heterojunctions

Abstract A perfect match of lattice constants is not normally possible in heterojunctions and, therefore, defects, mainly in the form of interfacial dislocations, are present at the heterojunctions interface. Experimental evidence for the electrical properties of isolated bulk dislocations, grain boundary dislocations and dangling bonds at surfaces, as well as at SiO 2 Si interfaces, suggests that interfacial defects at heterojunctions produce important effects. In particular, for lattice mismatches of about 1 per cent or greater, sufficient interface states should be created to bend the bands at the interface and, thus, largely determine the device characteristics. In addition, interfacial dislocations would be expected to cause severe minority carrier recombination, even for lattice mismatches of as low as 0·05 per cent. Therefore, efficient wide-gap-emitter action in Ge/GaAs p - n heterojunctions is likely to be difficult to achieve. The electrical characteristics of some n - n and p - p Ge/Si are reported and can be accounted for on the basis of a heterojunction theory including interface states. The electron affinity difference ( χ Ge - χ Si ) is 0·15 ± 0·03 eV as determined from the Ge/Si n - n structures.

Triggering phenomena in avalanche diodes

The operation of a small area p-n junction diode above the breakdown voltage is analyzed. A new formulation in terms of ionization probability is used to derive the rate of turn-on of current in such structures. Two differential equations are given which may be used to compute the probability that a carrier swept into or generated within the space-charge region triggers avalanche breakdown. For a 27-V n+-p diode biased 1 V above breakdown, this probability is close to 0.5 for an electron entering from the p side, or 0.1 for a hole entering from n side. Experimental measurements are in good agreement with the theoretical predictions.

n-n Semiconductor heterojunctions

Abstract Junctions between n -type semiconductors of different electron affinity show rectification if the junction is sufficiently abrupt. Such structures are potentially very fast, because only majority-carrier transport is involved. InPGaAs n-n junctions were fabricated with an epitaxial vapor-growth method. Typical V-I characteristics display a forward-voltage drop of 0·3 V at 10 A cm 2 , and a reverse leakage current of 0·5 A cm 2 at −2 V. No storage was observable in switching measurements on these devices. Other observations demonstrate that these junctions are indeed n-n heterojunction rectifiers. Ideal semiconductor-semiconductor contacts are reviewed and the concepts extended to graded contacts. An abruptness requirement for rectification to exist is developed on the basis of this ideal model for the effects of junction grading during fabrication. If D is the diffusion constant of the fastest moving lattice atom at the growth temperature, t the growth time, δ χ the total electron affinity change through the junction, and L D the Debye length on the low-electron affinity side, then for appreciable rectification to exist a condition which must be satisfied is Dt D 2 δ χ 10 kT .

A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etching

The extension of the general process simulator SAMPLE to plasma etching and metallization is described. The etching algorithm is divided into isotropic, anisotropic, and direct milling components and is suitable for modeling wet etching, plasma etching, reactive ion etching, and ion milling. Separate deposition algorithms are used for CVD, sputtering, and planetary deposition. With the extension, it is possible to use a simple keyword repertoire to simulate a sequence of photolithography, etching, and deposition steps to obtain device cross sections at each stage of fabrication.

Modeling of stress effects in silicon oxidation

A new set of models for the stress effects in silicon oxidation is proposed. The most essential feature is the nonlinear shear-stress-dependent oxide viscosity which models a high-stress relaxation phenomenon similar to plastic deformation. The models are shown to agree well with the most comprehensive and quantitative experimental data available-the thickness of oxide grown on both convex and concave cylindrical silicon structures. The model parameters are extracted by fitting the simulation of two-dimensional growth rates to the experimental values. The extracted values for the linear viscosity of wet oxide are shown to be close to independent data for the equilibrium viscosity of silica. Furthermore, the proposed oxide viscosity model with the extracted model parameters can successfully explain both the occurrence and the magnitude of the intrinsic stress in planar silicon oxidation. >

The mechanism of radiation-induced compaction in vitreous silica

We describe vitreous silica as a two-phase system. Low-temperature phase A and high-temperature phase B are connected by a solid-state phase transition and the phase transition temperature should be higher than the glass transition temperature. This model is based on the observed volume change induced by hydrostatic pressure, fast neutron, ion, electron and photon radiation, etc. Compaction induced by knock-on radiation in vitreous silica is different from compaction induced by ionizing radiation. For the latter, the observed stretched power dependence of compaction on deposited energy for ionization damage can be explained by applying a simple relaxation model.

Channeling effect of low energy boron implant in

Unintentional ion channeling in low energy ion implantation of boron into

Admittance of p-n junctions containing traps☆

Abstract A p-n junction containing large densities of deep levels is analyzed using a truncated space-charge approximation. The continuity equation for the occupation of deep levels is solved simultaneously with Poissons equation to obtain the frequency dependent capacitance of a junction containing one or more levels. That portion of the capacitance which enters the field-effect transconductance is also obtained and is found to have a different frequency dependence. An apparent dependence of the deep level time constant on compensation is shown to arise from the interaction between the total charge in the levels and the electron concentration in the space-charge region. This interaction further alters all the time constants when two or more deep levels are present. The single level theory is compared with the experiments and more exact numerical calculations of Sah and co-workers, and the two level theory is compared with experimental results on neutron-irradiated junction field-effect transistors.