Charles H. Fields

Shot-noise and edge roughness effects in resists patterned at 10 nm exposure

The experimental shot-noise effects and line-edge roughness are reported for two positive and two negative tone chemically amplified resists (IBM Apex-E, Shipley UVIIHS, IBM ENR, and Shipley SAL-601, respectively) produced by high resolution (10 nm) focused ion-beam exposure. Scanning electron micrographs at the resolution limit for each resist (50–70 nm) showed that the positive resists became negative in tone and that edge roughness was reasonable. Shot-noise effects causing arrays of 10 nm posts to print or not to print at exposure events of 7, 14, and 28 average ions per post were observed in SAL-601 and agree with Poisson statistics. Single exposure events were not observed in any resist possibly owing to the fact that the working minimum exposure level at the resolution limit of the resist material required several overlapping events to print.

A low power 52.9 GHz static divider implemented in a manufacturable 180 GHz AlInAs/InGaAs HBT IC technology

We have demonstrated a 52.9 GHz static 1/8 divider in an AlInAs/InGaAs HBT technology. To our knowledge this is the fastest static divider reported in any semiconductor technology. The divider was realized in a high yield optical lithography triple mesa HBT process. At maximum speed, power consumption was 40 mW/flip-flop. A second 1/8 divider, designed for lower power but using the same size transistors, consumed 8.6 mW/flip-flop at 35 GHz. Sensitivity was excellent with the high-speed version operating from DC to 48 GHz with less than 0 dBm input power. Uniformity and reproducibility were also demonstrated; all functional dividers operated above 45 GHz on-wafer and the extrapolated yield of dividers indicates that the process is capable of supporting 500-1000 transistor designs. Circuit performance was relatively insensitive to the details of the device epitaxial structure indicating a highly robust and manufacturable process.

A low power 72.8 GHz static frequency divider implemented in AlInAs/InGaAs HBT IC technology

We report a 72.8 GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than 0 dBm input power up to a maximum clock rate of 63 GHz and requires 86 dBm of input power at the minimum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1 V power supply. To our knowledge this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is also the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1 V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power delay product for a static divider operating above 30 GHz in any technology.

A low power (45mW/latch) static 150GHz CML divider

Operation of a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0.4/spl mu/m InP/InGaAs/InP DHBT technology, dissipates only 45mW per latch, and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies. On a full thickness wafer in a 27/spl deg/C ambient, the maximum operating frequency of the divider was 143.6GHz; this range extended to 151.2GHz when an air flow at -30/spl deg/C was established across the wafer.

Submicron AlInAs/InGaAs HBT with 160 GHz f/sub T/ at 1 mA collector current

We have demonstrated a submicron heterojunction bipolar transistor (SHBT) with a unity current gain cutoff frequency (f/sub t/) of 160 GHz at the very low current level of 1 mA. The AlInAs/InGaAs SHBT has a thin collector and uses stepper lithography with 0.1 /spl mu/m registration accuracy to reduce the parasitic elements that typically limit the performance of small transistors. The same device has 100 GHz f/sub t/ at 200 /spl mu/A. The result substantially improves upon the cutoff frequency of submicron compound semiconductor devices. The technology is appropriate for high speed, low power, high-density circuits.

38 GHz low phase noise CPW monolithic VCOs implemented in manufacturable AlInAs/InGaAs HBT IC technology

We have demonstrated a 38 GHz voltage controlled oscillator (VCO) with an integrated buffer amplifier in AlInAs/InGaAs HBT technology. Coplanar waveguide (CPW) circuit designs has been employed for the development of the InP HBT MMIC VCOs to reduce chip cost and make them flip chip compatible. The VCO was realized in a high yield optical lithography triple mesa HBT process. This VCO delivers a typical output power of 10 dBm at a center frequency of 38.4 GHz with a tuning range of up to 850 MHz. The measured phase noise shows -82 dBc/Hz at 100 khz offset and -1.08 dBc/Hz at 1 MHz offset. Uniformity and reproducibility were also demonstrated. Circuit performance was relatively insensitive to process variation indicating a highly robust and manufacturable circuit design and process.

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.

Effects of device design on the thermal properties of InP-based HBTs

The authors study the effects of thermal resistance in InP-based HBTs with different vertical and lateral design. 3D simulations and measurement results illustrate that significant differences in thermal resistance can arise with relatively small changes in device structure. These results also highlight the significant thermal gradients within the transistor.

A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping

Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, /spl Delta//spl Sigma/-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. These /spl Delta//spl Sigma/ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption.