William J. Song

Improvements to seamless vertical handover between mobile WiMAX and 3GPP UTRAN through the evolved packet core

Recent mobile devices are integrated with multiple network interfaces. Users want their devices connected to the network anytime anywhere. It is highly feasible for a user to change connection to another network for users that leave the service area of its current serving network, where handover needs to be executed seamlessly such that ongoing service sessions are not interrupted. The handover operation not only requires switching the interfaces within a device but also involves seamless reconfiguration of the supporting networks. In this article, an improved IP-based vertical handover technology for mobile WiMAX , 3GPP legacy systems (i.e., Global System for Mobile communications and Universal Mobile Telecommunications System), and 3G Long Term Evolution is presented, which is based on existing optimized handover techniques between mobile WiMAX and 3GPP accesses. Formerly proposed 3GPP WiMAX optimized VHO solutions introduced new elements, such as the forward attachment function and access network discovery and selection function. The ANDSF supports the discovery of target access, and the FAF provides the functionality that authenticates the UE before the execution of VHO. However, the previous technique has limitations that result in data loss and abnormal disconnection to the source access. This article provides a solution by introducing an additional network element called the data forwarding function (DFF) that eliminates the data loss during VHO execution. In addition, the DFF resolves the problem of abrupt disconnection to the source network. The simulation results show that the proposed VHO technique is effective in minimizing data loss during VHO execution between mobile WiMAX and 3GPP networks. As the proposed solution of this article is an IP based handover solution, it can be similarly applied to other communication networks.

Manifold: A parallel simulation framework for multicore systems

This paper presents Manifold, an open-source parallel simulation framework for multicore architectures. It consists of a parallel simulation kernel, a set of microarchitecture components, and an integrated library of power, thermal, reliability, and energy models. Using the components as building blocks, users can assemble multicore architecture simulation models and perform serial or parallel simulations to study the architectural and/or the physical characteristics of the models. Users can also create new components for Manifold or port existing models. Importantly, Manifolds component-based design provides the user with the ability to easily replace a component with another for efficient explorations of the design space. It also allows components to evolve independently and making it easy for simulators to incorporate new components as they become available. The distinguishing features of Manifold include i) transparent parallel execution, ii) integration of power, thermal, reliability, and energy models, iii) full system simulation, e.g., operating system and system binaries, and iv) component-based design. In this paper we provide a description of the software architecture of Manifold, and its main elements - a parallel multicore emulator front-end and a parallel component-based back-end timing model. We describe a few simulators that are built with Manifold components to illustrate its flexibility, and present test results of the scalability obtained on full-system simulation of coherent shared-memory multicore models with 16, 32, and 64 cores executing PARSEC and SPLASH-2 benchmarks.

A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration

We describe the integrated power, area and thermal modeling framework in the Structural Simulation Toolkit (SST) for large-scale high performance computer simulation. It integrates various power and thermal modeling tools and computes run-time energy dissipation for core, network on chip, memory controller and shared cache. It also has functionality to update the leakage power as temperature changes. We illustrate the utilization of the framework by applying it to explore interconnect options in manycore systems with consideration of temperature variation and leakage feedback. We compare power, energy-delay-area product (EDAP), and energy-delay product (EDP) of four manycore configurations-1 core, 2 cores, 4 cores and 8 cores per cluster. Results from simulation with or without consideration of temperature variation both show that the 4-core per cluster configuration has the best EDAP and EDP. Even so, considering temperature variation increases total power dissipation. We demonstrate the importance of considering temperature variation in the design ow. With this power, area and thermal modeling capability, SST can be used for hardware/software co-design of future Exascale systems.

Power Modeling for GPU Architectures Using McPAT

Graphics Processing Units (GPUs) are very popular for both graphics and general-purpose applications. Since GPUs operate many processing units and manage multiple levels of memory hierarchy, they consume a significant amount of power. Although several power models for CPUs are available, the power consumption of GPUs has not been studied much yet. In this article we develop a new power model for GPUs by utilizing McPAT, a CPU power tool. We generate initial power model data from McPAT with a detailed GPU configuration, and then adjust the models by comparing them with empirical data. We use the NVIDIAs Fermi architecture for building the power model, and our model estimates the GPU power consumption with an average error of 7.7% and 12.8% for the microbenchmarks and Merge benchmarks, respectively.

A power capping controller for multicore processors

This paper presents an online controller for tracking power-budgets in multicore processors using dynamic voltage-frequency scaling. The proposed control law comprises an integral controller whose gain is adjusted online based on the derivative of the power-frequency relationship. The control law is designed to achieve rapid settling time, and its tracking property is formally proven. Importantly, the controller design does not require off-line analysis of application workloads making it feasible for emerging heterogeneous and asymmetric multicore processors. Simulation results are presented for controlling power dissipation in multiple cores of an asymmetric multicore processor. Each core is i) equipped with the controller, ii) assigned a power budget, and iii) operates independently in tracking to its power budget. We use a cycle-level multi-core simulator driven by traces from SPEC2006 benchmarks demonstrating that the proposed algorithm achieves a faster settling time than examples of a static setting of the controller gain.

Throughput regulation in multicore processors via IPA

This paper presents an online controller for regulating the throughput of instruction-sequences in multicore processors using dynamic voltage-frequency scaling. The proposed control law comprises an integral controller whose gain is adjusted online based on the derivative of the frequency-throughput relationship. This relationship is modeled as a stochastic DEDS having no analytic functional form, and hence its derivative is estimated by Infinitesimal Perturbation Analysis (IPA). However, the DEDS is multi-class and hence the IPA derivative is biased. Biasedness of IPA is a common problem in multi-class DEDS which has hindered the development of IPA as a general tool for practical applications. However, recently it has been suggested that as long as the relative bias has certain upper bounds, optimization algorithms and control laws can still converge to optimal or near-optimal parameters. The purpose of this paper is to demonstrate this point for the aforementioned problem of throughput regulation, thereby suggesting the potential emergence of a new class of effective control laws in computer architectures.

Enhancements to FPMIPv6 for improved seamless vertical handover between LTE and heterogeneous access networks

Fast handovers for proxy mobile IPv6 (FPMIPv6) was created to reduce packet-delay that occurs during proxy mobile IPv6 (PMIPv6) handover. Based on vertical handover (VHO) experiments conducted between Long Term Evolution (LTE) and heterogeneous accesses over the evolved packet core (EPC) using FPMIPv6, it was recognized that consistently reliable seamless VHO operations were difficult to accomplish due to limitations in FPMIPv6. Noticeably, VHO performance degradation resulted from the serving network (SN) lacking information of the target network (TN) when the TN is a heterogeneous protocol domain, packet congestion and loss problems occurring on specific network gateway interfaces, and also from using long packet-forwarding paths. In this article, an enhanced FPMIPv6 technique is proposed to solve these problems and improve the VHO operation by using shorter data-paths and improved coordination of buffered packet-forwarding and TN switching, which results in a significantly reduced packet-delay.

Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors

This paper presents a lifetime reliability characterization of many-core processors based on a full-system simulation of integrated microarchitecture, power, thermal, and reliability models. Under normal operating conditions, our model and analysis reveal that the mean-time-to-failure of cores on the die show normal distribution. From the processor-level perspective, the key insight is that reducing the variance of the distribution can improve lifetime reliability by avoiding early failures. Based on this understanding, we present two variance reduction techniques for proactive reliability management; i) proportional dynamic voltage-frequency scaling (DVFS) and ii) coordinated thread swapping. A major advantage of using variance reduction techniques is that the improvement of system lifetime reliability can be achieved without adding design margins or spare components.

Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures

Sustaining processor performance growth is challenged by physical limitations due to increased power and heat dissipations. Power and thermal management techniques combined with inherent workload dynamics create the spatiotemporal variations of power, temperature, and degradation in processors. As industry moves to smaller feature sizes, the performance will become increasingly dominated by the physics. The challenge is in understanding how the physics is manifested at the microarchitecture level. This requires the modeling and simulation environment that can capture multiple, distinct physical phenomena and their concurrent impact on the microarchitecture.

Managing performance-reliability tradeoffs in multicore processors

There is a fundamental tradeoff between processor performance and lifetime reliability. High throughput operations increase power and heat dissipations that have adverse impacts on lifetime reliability. On the contrary, lifetime reliability favors low utilization to reduce stresses and avoid failures. A key challenge of understanding this tradeoff is in connecting application characteristics to device-level degradation behaviors. Using a full-system microarchitecture and physics simulation, the performance-reliability tradeoff in a multicore processor is analyzed by introducing a metric, throughput-lifetime product (TLP). A finding reveals that reducing the variance of degradation distribution on the multicore die leads to effectively enhancing processor lifetime with minimal impact on performance. This concept is referred to as dynamic reliability variance management (DRVM). We discuss three possible microarchitectural techniques that perform DRVM and improve the TLP; i) phase-aware thread migration, ii) dynamic voltage scaling, and iii) turbo-mode execution combined with DRVM. The simulation results with selected PARSEC and SPLASH-2 benchmarks show that DRVM techniques improve processor lifetime up to 15% or enhance the throughput-lifetime tradeoff by 12% without adding extra design margins or spare components on the multicore die.