Minki Cho

Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system

In this paper we present a test structure and design methodology for testing, characterization, and self-repair of TSVs in 3D ICs. The proposed structure can detect the signal degradation through TSVs due to resistive shorts and variations in TSV. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to improve signal fidelity. The paper presents the design of the test/recovery structure, the test methodologies, and demonstrates its effectiveness through stand alone simulations as well as in a full-chip physical design of a 3D IC.

Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System

In this paper, we present a methodology for characterization and repair of signal degradation in through-silicon-vias (TSVs) in 3-D integrated circuits (ICs). The proposed structure can detect the signal degradation through TSVs due to resistive shorts in liner oxide and variations in resistance of TSV due to weak open and/or bonding resistance. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to maintain signal fidelity. This allows electrical repair of TSVs with moderate defects leading to better design yield and system functionality. This paper presents the design of the test and recovery structure and demonstrates their effectiveness through stand alone simulations as well as in a full-chip physical design of a 3-D IC.

Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications

This paper presents a dynamically reconfigurable SRAM array for low-power mobile multimedia application. The proposed structure use a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits. The architecture allows reconfigure the number of bits in the low-voltage mode to change the error characteristics of the array in run-time. Simulations in predictive 70 nm nodes show that the proposed array can obtain 45% savings in memory power with a marginal (~10%) reduction in image quality.

Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications

We propose a dynamically reconfigurable SRAM architecture for low-power mobile multimedia applications. Parametric failures due to manufacturing variations limit the opportunities for power saving in SRAM. We show that, using a lower voltage for cells storing low-order bits and a nominal voltage for cells storing higher order bits, ~45% savings in memory power can be achieved with a marginal (~10%) reduction in image quality. A reconfigurable array structure is developed to dynamically reconfigure the number of bits in different voltage domains.

Proactive power migration to reduce maximum value and spatiotemporal non-uniformity of on-chip temperature distribution in homogeneous many-core processors

This paper presents a proactive spatiotemporal power multiplexing method to manage the thermal field in many-core processors. We first analyze the thermal field in many core processors in deep nanometer (to 16nm nodes). We show that the thermal field in many-core can have significant spatiotemporal non-uniformity along with high maximum temperature. For better reliability and improved cooling efficiency, it is important to achieve a lower peak temperature and a more uniform thermal field under all workload or utilization conditions. We propose proactive power migration to reduce spatial and temporal temperature difference, by redistributing the heat generating locations. The effectiveness of the proposed method is demonstrated for a 256 core many-core processor in predictive 16nm nodes.

Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration

We present adaptive spatiotemporal power migration (ASTPM) for burn-in of many core chips. ASTPM adapts the number of simultaneously stressed cores and dynamically varies their location to prevent thermal runaway, improve test-quality, and optimize burn-in time.

Characterization of Inverse Temperature Dependence in logic circuits

As the supply voltage (VDD) approaches the device threshold voltage (VT), the elevated temperature results in increased device current. This phenomenon is generally known as Inverse Temperature Dependence (ITD). In this paper, we propose a test structure with a built-in poly-resistor-based heater to characterize ITD in digital circuits. Our measurements from a 130nm test-chip show that the Zero-Temperature-Coefficient (ZTC) point varies by circuit type, and further fluctuates due to process variation. A more accurate ITD-sensitive thermal sensor is thus needed for better temperature tracking.

Thermal system identification (TSI): A methodology for post-silicon characterization and prediction of the transient thermal field in multicore chips

This paper presents a methodology for post-silicon thermal prediction to predict the transient thermal field a multicore package for various workload considering chip-to-chip variations in electrical and thermal properties. We use time-frequency duality to represent thermal system in frequency domain as a low-pass filter augmented with a positive feedback path for leakage-temperature interaction. This thermal system is identified through power/thermal measurements on a packaged IC and is used for post-silicon thermal prediction. The effectiveness of the proposed effort is presented considering a 64 core processor in predictive 22nm node and SPEC2006 benchmark applications.

Impact of die-to-die thermal coupling on the electrical characteristics of 3D stacked SRAM cache

We study the thermal coupling in a 3D stack with multiple cores in one tier and an SRAM array (cache) in a second tier with face-to-back bonding. For identical statistical distribution of power dissipation in cores, the SRAM sub-arrays experience much higher mean and variance in temperature in a 3D stack compared to a conventional 2D system. The increased variability in temperature increases leakage, degrades performance, and accelerates aging in 3D integrated SRAM. This is studied using 32nm predictive technology. Further, the spatial and temporal variations in performance of SRAM blocks become a strong function of the power variations in cores.

Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors

In this paper, a proactive thermal management technique called “power multiplexing” is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called “proximity index” which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing.