William James Biederman

A Fully-Integrated, Miniaturized (0.125 mm²) 10.5 µW Wireless Neural Sensor

A wirelessly powered 0.125 mm2 65 nm CMOS IC for Brain-Machine Interface applications integrates four 1.5 μW amplifiers (6.5 μVrms input-referred noise with 10 kHz bandwidth) with power conditioning and communication circuitry. The multi-node backscatter frequency locks to a wireless interrogator using a frequency-domain multiple access communication scheme. The full system, verified with wirelessly powered in vivo recordings, consumes 10.5 μW and operates at 1 mm range in air with 50 mW transmit power.

A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation

A 65 nm CMOS 4.78 mm 2 integrated neuromodulation SoC consumes 348 μA from an unregulated 1.2 V to 1.8 V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50 Hz and engaging two stimulators with a pulse width of 250 μs/phase, differential current of 150 μA, and a pulse frequency of 100 Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.

A Fully Integrated CMOS Accelerometer Using Bondwire Inertial Sensing

This paper presents the design, implementation, and characterization of a fully integrated accelerometer using a bondwire inertial sensor. The accelerometer was implemented in a standard CMOS process without microelectromechanical processing. The system consists of a gold and aluminum bondwire inertial sensor and readout circuitry. Finite-element analysis was used to characterize the mechanical performance of the accelerometer and reinforce empirical data. The system includes a fully differential frequency modulation downconversion architecture and consumes 13.5 mW while achieving a gain of 10 kHz/g, a bandwidth of 700 Hz, and a resolution of 80 mg. The chip was fabricated in an 0.13-m CMOS process with an area of 1.1 mm.

A CMOS switched-capacitor fractional bandgap reference

An architecture for generating a voltage reference at a fraction of the silicon bandgap is proposed. It uses a two-phase switched-capacitor network to add multiples and fractions of V_BE and ΔV_BE to achieve a near zero temperature coefficient without the use of resistors or op-amps. The 0.0055mm² circuit, implemented entirely on-chip in 65nm CMOS, produces a voltage of 423mV, has a measured σ of 2.2%, and consumes 138nA while operating at a supply as low as 750mV at -35°C.

A 4.78mm 2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation

A 65nm CMOS 4.78mm 2 integrated neuromodulation SoC consumes 417μW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250μs/phase, differential current of 150μA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.

A fully-integrated 10.5µW miniaturized (0.125mm 2 ) wireless neural sensor

A wirelessly powered 0.125mm2 65nm CMOS IC for BMI applications integrates four 1.5μW amplifiers (6.5μVrms input-referred noise for a 10kHz bandwidth) with power conditioning and communication circuitry. The multi-node backscatter FDMA communication scheme frequency locks to a wireless interrogator. The full system, verified wirelessly with MATLAB generated neural data, consumes 10.5μW, and operates at 1mm range in air with 50mW transmit power.