Augusto Marques

A 12-bit intrinsic accuracy high-speed CMOS DAC

A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 /spl mu/m CMOS technology is presented. It is based on a current steering doubly segmented 6+2+4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSBs), respectively. The measured glitch energy is 1.9 pV.s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm/sup 2/.

A 900-mV low-power /spl Delta//spl Sigma/ A/D converter with 77-dB dynamic range

The design of a low-voltage and low-power /spl Delta//spl Sigma/ analog-to-digital (A/D) converter is presented. A third-order single-loop /spl Delta//spl Sigma/ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV /spl Delta//spl Sigma/ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-/spl mu/W power consumption.

A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications

The design of a high-resolution high-speed delta-sigma analog-to-digital converter that operates from a single 3.3V supply is presented. This supply voltage presents several design problems, such as the reduced signal swing and the non-zero switch-resistance in the switched-capacitor circuits. These problems are tackled in this design without the use of special circuit techniques, such as clock-boosters. The converter uses a 2-1-1 cascade topology with optimised coefficients. For an oversampling-ratio of only 24, the converter achieves a SNR of 87 dB, a SNDR of 82 dB and an input dynamic range of 15 bits after comb-filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for ADSL-applications of 1.1 MHz. It is implemented in a 0.5 µm CMOS technology, in a 5 mm2die-area and it consumes 200 mW from a 3.3 V power supply.

Optimal parameters for /spl Delta//spl Sigma/ modulator topologies

A systematic study of single-loop, cascaded, and multibit /spl Delta//spl Sigma/ modulators of second to fourth order is presented, based on a combination of behavioral simulations and linear modeling. Constraints for optimal performance and precise guidelines for the choice of parameters are derived. Moreover, the optimal parameters and the corresponding performance are found and given in tables. A graph showing the maximal achievable performance of each topology as a function of the oversampling ratio is presented, offering a valuable help for the design of analog-to-digital converters.

A 15-b resolution 2-MHz Nyquist rate /spl Delta//spl Sigma/ ADC in a 1-/spl mu/m CMOS technology

A high-resolution high-speed fourth-order cascaded /spl Delta//spl Sigma/ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-/spl mu/m CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage.

A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (signal to noise plus distortion) is over 30 dB at 500 MHz clock and f/sub IN/=141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30 dB. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology with double poly and occupies an active area of 0.8 mm/sup 2/.

A 12 bit 200 MHz low glitch CMOS D/A converter

A 12-bit 200 MHz CMOS current steering D/A converter is presented. The measured glitch energy is 0.8 pVs. To obtain this very low glitch energy specification, a new driver circuit using a dynamic latch is proposed. The measured INL is better than +/-0.5 LSB. The D/A converter operates at a 2.7 V power supply, it has a 20 mA full swing output current and a 200 MHz conversion rate. The worst case power consumption is 140 mW at the maximum conversion rate. The chip has been processed in a standard 0.5 /spl mu/m CMOS technology.

Settling time analysis of third order systems

Several operational transconductance amplifiers often have a third order transfer function. The use of these amplifiers for several applications, such as in switched-capacitor circuits requires the minimization of the settling time to a step response. This problem is studied in this work. First, the closed loop transfer function of a system with an the open loop 3/sup rd/ order transfer function is obtained, and a mapping from the closed loop parameters to the open loop parameters is derived. Second, the closed loop step response is deduced. Third, the dynamic settling error is studied based on numerical simulations. The described procedure can be used to find the optimal location for the open loop poles and zeros that minimizes the settling time for a specific amplifier structure.

A 12 b accuracy 300 Msample/s update rate CMOS DAC

Of several technology and architecture alternatives for >100 MHz >10 b DACs, CMOS current-steering DAC architectures are particularly suitable. (1) They can be designed in a standard digital CMOS technology, with evident cost and power consumption advantages in the integration with the digital circuits, and (2) They are intrinsically faster and more linear than competing architectures such as resistor-string DACs. This DAC is integrated in a standard digital 0.5 /spl mu/m CMOS technology. It has a current steering 6+2+4 segmented architecture: first, the six most significant bits (MSBs) are linearly decoded; second, the intermediate two bits are also linearly decoded, but independently from the MSBs; third, the four least significant bits are binary weighted.

A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications

The design of a high-resolution high-speed delta-sigma analog-to-digital converter that operates from a single 3.3V supply is presented. This supply voltage presents several design problems, such as the reduced signal swing and the non-zero switch-resistance in the switched-capacitor circuits. These problems are tackled in this design without the use of special circuit techniques, such as clock-boosters. The converter uses a 2-1-1 cascade topology with optimised coefficients. For an oversampling-ratio of only 24, the converter achieves a SNR of 87 dB, a SNDR of 82 dB and an input dynamic range of 15 bits after comb-filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for ADSL-applications of 1.1 MHz. It is implemented in a 0.5 µm CMOS technology, in a 5 mm2die-area and it consumes 200 mW from a 3.3 V power supply.