Seongmo Park

Fast motion estimation with adaptive search range adjustment

A fast motion estimation algorithm based on the adaptive search range adjustment (ASRA) is presented. The size of search range for each block is adaptively controlled according to the initial cost at the search center, and then the full search algorithm (FSA) is performed to find the optimal matching block in the adjusted search range. The proposed method is implemented in H.264/AVC reference software (JM) to demonstrate its efficiency over the conventional FSA.

An implemented of H.264 video decoder using hardware and software

In this paper, we present a design of video single chip decoder for portable multimedia application. The single- chip called as A-MoVa (advanced mobile video ASIC). This chip has mixed hardware/software architecture to combine performance and flexibility. We designed by using the partition between hardware and software block. We developed the architecture of H.264 decoder based on SoC platform. This chip contains 290,000 gates of logics, 670,000 gates of memories and the chip size was 7.5 mm times 7.5 mm which was fabricated using 0.25 micron 4-layers metal CMOS technology

Novel RT level methodology for low power by using wasting toggle rate based clock gating

In this paper, we propose a RT level power reduction scheme which can be used for the applications that require ultra-low power consumption. A novel wasting-toggle-rate (WTR) based clock power reduction technique is introduced. It compares the WTR of a stimulus with the pre-computed threshold WTR of the circuit, and clock gating is applied to the circuit only if there is power-saving benefit. It considers not only clock enable signal, but also data signal and wasting toggle rate of the clock in a fine-grained manner. The proposed technique is implemented at RT level in a complete CAD solution. We have tested the proposed technique on real industrial multimedia-mobile-processor design. For the accuracy of the power optimization results, all the power estimation results are measured at gate level after synthesis by using industrial 65 and 90 nanometer technology libraries. The experimental results show that using 65 nanometer technology, the technique reduces 35.46% power comparing with non-clock gating design and 18.80% power comparing with clock-gating design by Power Compiler; and that using 90 nanometer technology, the technique reduces average 39.34% total power comparing with non-clock gating design and 27.76% total power comparing with clock-gating design by Power Compiler. For the design overhead of the proposed technique, it increases 1.17% of the critical path delay and reduces 0.81% of the area for the whole circuit comparing with the original circuit in 65 nanometer technology, and increases 2.75% of the critical path delay and reduces 0.75% area for whole circuit in 90 nanometer technology.

Implementation of 3D graphics accelerator using full pipeline scheme on FPGA

This paper proposes effective 3D graphics hardware. It is designed to support the OpenGL ES 2.0 and Shader model 3.0. We develop all module (vertex shader, clipping engine, triangle setup engine, rasterizer, pixel shader and raster operator) of 3D pipeline on FPGA using RTL design. The proposed hardware of which total gate count is about 1.486 M operates with 100 Mpixels/sec at pixel shader. Compared to the other product of a company, the proposed architecture result in about 50% improvement in term of cycle.

Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism

In order for the video decoding processing such as H.264 and VC-1 to be effective in multi-core environments, several kinds of parallelisms must be utilised. Here, a novel parallelisation methodology, macroblock row-level parallelism (MBRLP), of video decoding is presented. The ETRI multimedia processing core (EMC) and the ETRI multi-core platform (EMP) are proposed for adopting MBRLP. In terms of the scalability and utilisation of processing cores, MBRLP has advantages over other parallelisation strategies such as frame, slice and macroblock (MB)-level parallelism. The scalability can be easily achieved by just increasing the number of processing cores and applying homogeneous software design/optimisation techniques to each EMC. Instead of employing a dynamic MB-level scheduler, a hybrid approach is used, which is a two-stage functional pipelining combined with MBRLP. The hybrid approach of combining MBRLP and de-blocking pipelining can relieve the synchronisation and inter-processor communication overheads incurred by multicore decoding systems as well as run-time schedulers overheads. As a result, the proposed parallelisation method and architectures can boost the performance with the efficiency of 83%. The proposed architecture consisting of six EMC clusters has the capability to process Dl (720 × 480) 30 fps real-time decoding at around 200 MHz. The same concept can be applied to full-HD (1920 × 1088) video decoding in this work. It can be found that as the number of processing cores increase, the performance improvement is enhanced almost linearly. The EMP consisting of four EMC clusters (eight cores), memories and other peripherals are prototyped on Xilinx Virtex4 XC4VL200 FPGA which is operating at 60 MHz.

SeSCG: Selective sequential clock gating for ultra-low-power multimedia mobile processor design

For ultra-low-power multimedia mobile processor (MMP) design, clock-power reduction is critical because the largest portion of the total power (more than 60% in the processor designs used in this paper) is consumed in the sequential logic. Currently, for the clock-power reduction, traditional combinational clock gating scheme has been used in industry and recently, sequential clock gating method is introduced by a few advanced CAD vendors. In order to maximize the power reduction of the MMP design, we propose a novel selective sequential clock gating (SeSCG) technique in this paper. The SeSCG scheme can choose optimal sequential clock gating style selectively for ultra-low-power design based on the proposed toggle rate analysis at RT level. We have tested the proposed technique on two real industrial MMP designs using 65 nanometer technology. The experimental results show that the conventional sequential clock gating scheme even increases average 4.77% of total power while the proposed SeSCG technique decreases average 23.71% total power with reasonably very small area overhead (no more than 0.63%) when we use real industrial testbenches for the two industrial MMP designs.

An area efficient video/audio codec for portable multimedia application

In this paper, we present an area efficient video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as VASP (Video Audio Signal Processor) consists of a video signal processing block and an audio signal processing block. This chip has a mixed hardware/software architecture to combine performance and flexibility. The video signal processing block was designed to implement hardwired solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bit RISC type internal controller. The audio signal processing block is implemented with a software solution using 16 bit fixed point DSP. This chip contains 142,300 gates, 22 kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size was 9.02 mm/spl times/9.06 mm which was fabricated using 0.5 micron 3-layers metal CMOS technology.

Reusable design of run length coder for image compression application

In this paper, we describe the interface specification and core block design methods for a run length coder of video compression application. It offers high performance and many features to meet multimedia, and digital video applications. We designed the VLSI architecture of the run length coder using VHDL. This design can achieve a high performance for the video coder and is based on H.263 Recommendation. The format of the outputs is compatible with the stream of the variable length coding. The run length coder is implemented by the register transfer level (RTL) of VHDL. The designed block is synthesized by Compass synthesis with 0.5 /spl mu/m CMOS, 3.3 V, technology and reuse as core IP (Intellectual Property) of H.263 and MPEG4 application. The run length coder block contains 4,000 logic gates and a total 1,536 bits of static RAM. The fully synchronous design allows for fast operation while maintaining a low gate count. The core will reuse for multimedia system and digital video applications.

Pipeline power reduction through single comparator-based clock gating

Enable-based Clock Gating (ECG) during synthesis to reduce the pipeline power consumption is widely used in scaled technologies. However, the ECG does not provide optimal solution at all in terms of power because it is synthesized by a global way and it does not consider the correlation between clock-enable signal and data signal. We propose a novel single comparator-based clock gating (SCCG) scheme to enhance the ECG for pipeline. In the proposed SCCG, enable signal is moved from data path to control logic, the data signal is analyzed, and only single comparator is used to implement the clock-gating for all the pipeline stages. Simulation results show that our proposed SCCG can save average 47.03% of total power with small 4-stage pipeline benchmark and can save 11.3% of total power with industrial multimedia-mobile processor design by using 90 nm industrial technology library comparing with the ECG-based designs.

Selective clock gating by using wasting toggle rate

In this paper, we propose a RT level power reduction scheme which can be used for any applications that have power problem when designers use traditional design flow. A novel wasting-toggle-rate based clock power reduction technique is introduced and verified along with traditional design flow. The proposed technique can choose optimal clock-gating style selectively to minimize the power based on proposed wastingtoggle-rate analysis at RT level, and the optimization is based on proposed power equations without simulating the design at gate level. We have tested the proposed technique on real industrial multimedia-mobile-processor design. For the accuracy of the power optimization results, all of them are measured at gate level after synthesis by using industrial 65 nanometer technology library. The experimental results show that the technique reduces average 35.84% power comparing with non-clock gating design and 19.28% power comparing with clock-gating design by Power Compiler. The design overhead of the proposed technique is 1.79% increase of area and 2.55% increase of the critical path delay for whole circuit comparing with the original circuit.