Wira Hidayat Mohd Saad

Design and optimization of TiSi x /HfO 2 channel vertical double gate NMOS device

This paper aims to propose a new structure of vertical double-gate NMOS device with titanium silicide (TiSi_x) and hafnium dioxide (HfO₂) are utilized as gates and an insulator correspondingly. The simulation and characterization of the proposed device were carried out by using ATHENA and ATLAS modules of Silvaco TCAD tools. The threshold voltage (V_TH) of the device was then optimized by tuning the correct level of halo implant dose, halo implant tilt, S/D implant energy and S/D implant tilt via the L₉ orthogonal array (OA) of Taguchi method. The vertical TiSi_x/HfO₂ channel vertical double-gate NMOS device has shown excellent device characteristics as the V_TH, drive current (I_ON), leakage current (I_OFF), I_ON/I_OFF ratio and subthreshold swing (SS) were observed to be 0.2101 V, 2235.3 μA/μm, 1.363E-15 A/μm, 1.64E12 and 58.76 mV/dec respectively. These results are within the expected requirement of high performance (HP) multi gate (MG) technology as predicted by International Technology Roadmap Semiconductor (ITRS) 2013.

Multi-response optimization in vertical double gate PMOS device using Taguchi method and grey relational analysis

Miniturization of MOSFET device leads to statistical variation of many process parameters that may cause the degradation of the device performance. Taguchi method has been applied as a tool to optimize the process parameter variation. Since, Taguchi method is only limited to the solution of a single response, it is combined with grey relational analysis (GRA) to solve multi-response optimization. This paper presents a proposed method to optimize halo implant energy, halo implant tilt angle, source/drain (S/D) implant energy and source/drain (S/D) implant tilt angle upon multiple performance characteristics of WSix/TiO2 channel vertical double-gate PMOS device. The normalized experimental results based on L9 Taguchi method are utilized to compute grey relational coefficients and grades. The final results show that the process parameters have been successfully optimized in obtaining a nominal threshold voltage (-0.1783 V), a high drive current (1539.1 μA/μm) and a low leakage current (6.749E-11 A/μm) which meet the International Technology Roadmap Semiconductor (ITRS) 2013 prediction for high performance logic multi-gate technology.