F. Salehuddin

Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor

In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchis nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

Optimization of input process parameters variation on threshold voltage in 45 nm NMOS device

In this study, Taguchi method was used to optimize the influence of process parameter variations on threshold voltage (V TH ) in 45 nm n-channel metal oxide semiconductor (NMOS) device. The orthogonal array, the signal-to-noise ratio, and analysis of variance were employed to study the performance characteristics of a device. In this paper, eleven process parameters (control factors) were varied for 2 levels to perform 12 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of V TH for every row of experiment. V TH results were used as the evaluation variable. This work was done using technology computer-aided design (TCAD) simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, compensation implantation energy was identified as one of the process parameters that have the strongest effect on the response characteristics. While the halo implantation dosage was identified as an adjustment factor to get the nominal values of threshold voltage for NMOS device equal to 0.176 V.

Analyze and optimize the silicide thickness in 45nm CMOS technology using Taguchi method

Taguchi method was used to analyze the experimental data in order to get the optimum average of silicide thickness in 45nm devices. The virtually fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were used as design tools and helps to reduce design time and cost. In this paper, both modules and Taguchi method was combined to aid in design and optimizer the process parameters. There are four process parameters (factors), namely Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. These factors were varied for 3 levels to perform 9 experiments. Threshold voltage (VTH) results were used as the evaluation variables. Then, the results were subjected to the Taguchi method for determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were successfully verified with ATHENA and ATLASs simulator. The results show that the average of silicide thickness after optimizations approaches was 30.66nm and 30.58nm for NMOS and PMOS devices respectively. In this research, Halo Implantation was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as an adjustment factor to get the nominal values of threshold voltage for PMOS and NMOS devices equal to −0.1501V and +0.150047V respectively.

Cobalt silicide and titanium silicide effects on nano devices

This paper describes growth process of the two silicide Sub-nanometer devices and the different effects of having cobalt silicide and titanium silicide on a Sub-nanometer CMOS devices. On the top of CMOS device gate, metal silicide is developed on-top of the polysilicon to produce an ohmic contact between the polysilicon and aluminum wire. The ohmic contact should be better compared to metal-polysilicon borders. This silicide has been widely used to reduce resistance of polysilicon gates. Metal silicides such as titanium silicide (TiSi2), tungsten salicide (WSi2), cobalt salicide (CoSi2) andnickel salicide (NiSi2) are widely used for this purpose. These metals react with polysilicon, to form metal silicide layer that possesses better physical and electrical properties to interface with aluminium. The silicide need to be optimally annealed in order to obtain a good ratio of metal silicide to silicon in the gate structure Titanium silicide is formed by depositing PVD Ti on silicon substrates followed by annealing process. Anneals were carried out in an N2 ambient and resulted in a thin TiN layer on the silicide surface. For cobalt cilicide, a CVD cobalt layer was deposited on-top silicon at 450°C, and after annealing the structure, Co2Si phase was formed. And at 800°C the high resistivity CoSi phase formed. As we continued to increase the anneal temperature to 950°C, CoSi2 layer is formed. The high temperature required to form a silicide and the non existence of the Co2Si phase are attributed to the oxide at the interface. It is found that cobalt silicide grew faster and deeper to the silicon, thus saving a lot of time and cost. The succeding experiments also show that cobalt silicide has better electrical properties such as sheet resistance, capacitance and electron mobility. The transistor fabrication process was simulated by using Silvaco ATHENA module and the resulting electrical characterization was simulated using ATLAS module

Impact of Different Dose and Angle in HALO Structure for 45nm NMOS Device

In this paper, we investigates the different dose and tilt HALO implant step in order to characterize the 45nm NMOS device. Besides HALO, the other two process parameters are oxide growth temperature and source/drain (S/D) implant dose. The settings of process parameters were determined by using Taguchi experimental design method. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimizer the process parameters. Threshold voltage (VTH) results were used as the evaluation variable. The results were then subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. In this research, oxide growth temperature was the major factor affecting the threshold voltage (69%), whereas halo implant tilt was the second ranking factor (20%). The percent effect on Signal-to-Noice (S/N) ratio of halo implant dose and S/D implant dose are 6% and 5% respectively. As conclusions, oxide growth temperature and halo implant tilt were identified as the process parameters that have strongest effect on the response characteristics. While S/D implant dose was identified as an adjustment factor to get threshold voltage for NMOS device closer to the nominal value (0.150V) at tox= 1.1nm.

Statistical process modelling for 32nm high-K/metal gate PMOS device

The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moores Law. In this paper, the design, fabrication and characterization of 32nm HfO₂/TiSi₂ PMOS device is presented; replacing the conventional SiO₂ dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (V_TH) and leakage current (I_OFF). The simulation result shows that the optimal value of V_TH and I_OFF which are 0.1030075V and 3.4264075×10^-12A/um respectively are well within ITRS prediction.

Effect of process parameter variations on threshold voltage in 45nm NMOS device

Taguchi method was used to optimize of the effect process parameter variations on threshold voltage in 45nm NMOS device. In this paper, there are four process parameters (factors) were used, which are Halo Implantation, Source/Drain (S/D) Implantation, Oxide Growth Temperature and Silicide Anneal temperature. The virtual fabrication of the devices was performed by using ATHENA module. While the electrical characterization of the devices was implemented by using ATLAS module. These two modules were combined with Taguchi method to aid in design and optimizer the process parameters. Threshold voltage (VTH) results were used as the evaluation variables. The results were then subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. The predicted values of the process parameters were then successfully verified with ATHENA and ATLASs simulator. In this research, oxide growth temperature was identified as one of the process parameters that has the strongest effect on the response characteristics. While the S/D Implantation was identified as adjustment factor to get the nominal values of threshold voltage for NMOS device equal to 0.15V.

Characterization and optimizations of silicide thickness in 45nm pMOS device

The characteristics of high performance 45nm pMOS devices based on International Technology Roadmap for Semiconductor (ITRS) have been studied using ATHENA and ATLASs simulator. There are four factors were varied for 3 levels to perform 9 experiments. The factors are halo implantation, Source/Drain (S/D) implantation, oxide growth temperature and silicide anneal temperature. In this paper, Taguchi Method was used to analyze the experimental data in order to get the optimum solutions for these factors. The silicide on the poly-Si gate electrode has been used to reduce the gate electrode resistance. The result shows that the threshold voltage (VTH) value is −0.1501 Volts. The value is exactly same with ITRS prediction. This shows that Taguchi Method is a very useful tool to predict the optimum solution in finding the 45nm pMOS fabrication recipes with appropriate VTH value. The result also shows that the average of silicide thickness after optimizations approaches is 30.12nm.

Analysis of threshold voltage variance in 45nm n-channel device using L27 orthogonal array method

In this research, orthogonal array of L27 in Taguchi Method was used to optimize the process parameters (control factors) variation in 45nm n-channel device with considering the interaction effect. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the device. There are only five process parameters (control factors) were varied for 3 levels to performed 27 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of Vth for every row of experiment. In this study, nominal-the-best characteristic was used in an effort to minimize the variance of Vth. The results show that the Vth values have least variance and percent different from the target value (0.287V) for this device is 1.42% (0.293V). This value is closer with International Technology Roadmap for Semiconductor (ITRS) prediction.

Analysis of process parameter effect on DIBL in n-channel MOSFET device using L27 orthogonal array

In this research, the effect of the process parameters variation on drain induced barrier lowering (DIBL) was investigated. The fabrication of the transistor device was performed using TCAD simulator, consisting of ATHENA and ATLAS modules. These two modules were combined with Taguchi method to optimize the process parameters. The setting of process parameters was determined by using the orthogonal array of L27 in Taguchi Method. In NMOS device, the most dominant or significant factors for S/N Ratio are halo implant energy, S/D implant dose and S/D implant energy. Meanwhile, the S/N Ratio values of DIBL after the optimization approaches for array L27 is 29.42 dB. In L27 experiments, DIBL value for n-channel MOSFET device after optimizations approaches is +37.8 mV. The results obtained were satisfied to be small as expected. As conclusions, by setting up design of experiment with the Taguchi Method and TCAD simulator, the optimal solutions on DIBL for the robust design recipe of 32nm n-channel MOSFET devic...