Zahariah Manap

A Review on Hierarchical Routing Protocols for Wireless Sensor Networks

The routing protocol for Wireless Sensor Networks (WSNs) is defined as the manner of data dissemination from the network field (source) to the base station (destination). Based on the network topology, there are two types of routing protocols in WSNs, they are namely flat routing protocols and hierarchical routing protocols. Hierarchical routing protocols (HRPs) are more energy efficient and scalable compared to flat routing protocols. This paper discusses how topology management and network application influence the performance of cluster-based and chain-based hierarchical networks. It reviews the basic features of sensor connectivity issues such as power control in topology set-up, sleep/idle pairing and data transmission control that are used in five common HRPs, and it also examines their impact on the protocol performance. A good picture of their respective performances give an indication how network applications, i.e whether reactive or proactive, and topology management i.e. whether centralized or distributed would determine the network performance. Finally, from the ensuring discussion, it is shown that the chain-based HRPs guarantee a longer network lifetime compared to cluster-based HRPs by three to five times.

Design and optimization of TiSi x /HfO 2 channel vertical double gate NMOS device

This paper aims to propose a new structure of vertical double-gate NMOS device with titanium silicide (TiSi_x) and hafnium dioxide (HfO₂) are utilized as gates and an insulator correspondingly. The simulation and characterization of the proposed device were carried out by using ATHENA and ATLAS modules of Silvaco TCAD tools. The threshold voltage (V_TH) of the device was then optimized by tuning the correct level of halo implant dose, halo implant tilt, S/D implant energy and S/D implant tilt via the L₉ orthogonal array (OA) of Taguchi method. The vertical TiSi_x/HfO₂ channel vertical double-gate NMOS device has shown excellent device characteristics as the V_TH, drive current (I_ON), leakage current (I_OFF), I_ON/I_OFF ratio and subthreshold swing (SS) were observed to be 0.2101 V, 2235.3 μA/μm, 1.363E-15 A/μm, 1.64E12 and 58.76 mV/dec respectively. These results are within the expected requirement of high performance (HP) multi gate (MG) technology as predicted by International Technology Roadmap Semiconductor (ITRS) 2013.

Analyze of threshold voltage in SOI PMOSFET device using Taguchi method

The short-channel effect (SCE) is the main problem of many metal-oxide-semiconductor field-effect transistor (MOSFET) industries. A lot of studies addressing the SCE effect have been conducted. One of the methods used for this is called SOI (silicon-on-insulator) technology. This method has been proven to effectively reduce the SCE effect. In this research paper, the electrical characteristic of an 18 nm gate length SOI PMOSFET was analyzed based on the prediction of the International Technology Roadmap for Semiconductors (ITRS). The threshold voltage would be the key characteristic in this research. Four process parameters were used with two noise factors in order to conduct nine sets of experiments using the L9 orthogonal array Taguchi method. At the end of the experiment, the best setting that was predicted by the Taguchi method would be utilized for the purpose of verification. The result shows that VTH after the optimization approach is closer to the nominal value (-0.533V), that is, within the appropriate range of ITRS 2013.

Multi-response optimization in vertical double gate PMOS device using Taguchi method and grey relational analysis

Miniturization of MOSFET device leads to statistical variation of many process parameters that may cause the degradation of the device performance. Taguchi method has been applied as a tool to optimize the process parameter variation. Since, Taguchi method is only limited to the solution of a single response, it is combined with grey relational analysis (GRA) to solve multi-response optimization. This paper presents a proposed method to optimize halo implant energy, halo implant tilt angle, source/drain (S/D) implant energy and source/drain (S/D) implant tilt angle upon multiple performance characteristics of WSix/TiO2 channel vertical double-gate PMOS device. The normalized experimental results based on L9 Taguchi method are utilized to compute grey relational coefficients and grades. The final results show that the process parameters have been successfully optimized in obtaining a nominal threshold voltage (-0.1783 V), a high drive current (1539.1 μA/μm) and a low leakage current (6.749E-11 A/μm) which meet the International Technology Roadmap Semiconductor (ITRS) 2013 prediction for high performance logic multi-gate technology.