Chris Iannello

Full bridge ZCS PWM converter for high-voltage high-power applications

This paper presents a comprehensive study of a full bridge (FB) zero-current switched (ZCS) PWM converter which is suitable for high-voltage and high-power DC application that achieves ZCS for all active switches, and zero-voltage-switched (ZVS) operation for all diodes on the high voltage side. The given converter utilizes component parasitic parameters, particularly for the high-voltage transformer, and employs fixed-frequency phase-shift control to implement soft-switching commutations. Detailed steady state analysis of the converter power stage is presented for the first time and the major features of the converters power stage are discussed. Small-signal characteristics are also presented and accompanied by a discussion of the controller design and implementation. A design example is also presented based on the steady state analysis and is validated by simulation. Theoretical and simulated results are in good agreement.

Small-signal and transient analysis of a full-bridge, zero-current-switched PWM converter using an average model

This paper presents a detailed small-signal and transient analysis of a full bridge zero-current-switched (FB-ZCS) PWM converter designed for high voltage, high power applications using an average model. The development shows the model follows directly from the converters steady-state analysis and is produced by inspection of the converters instantaneous waveforms. The method used in model development can be extended to other topologies that are not easily modeled by conventional methods. The derived model is implemented in a PSPICE subcircuit and used to produce the small-signal and transient characteristics of the converter. Results obtained in the analysis of the high voltage and high power design example are validated by comparison to the actual, switched-circuit simulations.

Window-Masked Segmented Digital Clock Manager-FPGA-Based Digital Pulsewidth Modulator Technique

This paper presents a new digital pulsewidth modulator (DPWM) architecture for field programmable gate array (FPGA)-based systems. The design of the proposed DPWM architecture is based on fully utilizing the digital clock manager (DCM) resources available on new FPGA boards. Furthermore, this architecture will also window-mask the DCM operation to only a portion of the switching period in order to decrease power dissipation. This proposed digital modulator technique allows for higher DPWM resolution with lower power consumption, the primary barrier to high switching frequency operation. The presented technique relies on power-optimized resources already existing on new FPGAs, and benefits from the inherit phase-shifting properties of the DCM blocks, which help in simplifying the duty cycle generation. The architecture can be applied to achieve different numbers of bits for the DPWM resolution designed for different dc-dc applications. The suggested architecture is first simulated, implemented, and experimentally verified on a Virtex-4 FPGA board.

Modeling of conduction losses in PWM converters operating in discontinuous conduction mode

In this paper, a non-ideal PWM switch model considering conduction losses is developed. This issue was considered in the past only with the assumption that the inductor current ripple is negligible compared with its average value. Derivation of the new model is based on the energy loss invariant principle. The resulting model can be applied to simulating large inductor current ripple conditions. Accuracy of the proposed model is verified through Pspice simulation using the buck and boost converters.

Segmented Digital Clock Manager- FPGA based Digital Pulse Width Modulator Technique

A new digital pulse width modulator (DPWM) design for a field programmable gate array (FPGA) based systems is presented in this paper. The proposed architecture fully utilizes the digital clock manager (DCM) resources available on new FPGA boards. The proposed segmented DCM DPWM is a digital modulator architecture with low power that allows for high switching frequency operation. It relies on the power-optimized resources already existing on new FPGAs. The inherit phase shifting properties of the DCM blocks simplify the duty cycle generation. The architecture can be applied to achieve various number of bits for the DPWM resolution, and is implemented and verified experimentally on a Virtex4 FPGA board.

A full bridge ZCS PWM converter for high voltage and high power applications

This paper presents the detailed analysis of a full bridge zero current switched (FB-ZCS) PWM converter that is suitable for high-voltage and high-power DC applications. It exhibits excellent ability to incorporate parasitic parameters, zero current turn-off characteristics for all active switches and ZVS operation for all diodes on the high voltage side. Based on the features of high-voltage power supplies, the converter utilizes parasitic components, particularly for the high-voltage transformer, and employs fixed frequency phase-shift control to implement soft-switching commutations. Steady state analysis of the converter is presented and major features of the converter are discussed. Finally, a small signal model based on the averaging method is created and the simulated results for typical traveling wave tube (TWT) load are given.

Closed-loop design for two parallel connected converters with power factor correction

A large signal simulation for two parallel converters in a distributed power supply system is presented in this paper. The distributed system is composed of switched-mode power factor correction (PFC) converters utilizing a central limit control technique. This technique allows one voltage loop compensator to be shared by all the PFC converters. Design of such a compensator is discussed and the system performances with regard to unequal cable resistances and load changes are reported. The resulting system achieves a power factor of about 0.98 and provides an excellent current sharing between the two converter modules.

Dynamic DC ramp shift digital control technique for improved transient response

A new control scheme aiming to improve the dynamic behavior of digitally controlled DC-DC converters in terms of improved settling time and overshoot is presented in this paper. The proposed approach enhances the transient response by dynamically controlling the ramp of the Digital Pulse Width Modulator (DPWM) unit by applying DC shift to the conventional ramp-based PWM during load change. This will help the compensator reach the steady-state value faster. The dynamic DC ramp shift design method presented in this paper utilizes the existing system digital controller, and does not require any additional circuitry. The presented control scheme is first analyzed, then simulated and finally experimentally verified using a DSP implementation.

Optimization design of a single-stage AC-DC converter with averaging circuit model and MathCAD/sup /spl copy//

Based on the averaging circuit model and MathCAD tool, a design optimization methodology for power factor correction circuits is presented in this paper. It is shown that such design optimization can be applied to most single-stage (S/sup 2/) converters. Both theoretical and experimental results are verified based on a 150 W prototype at 28 V output. Major performance comparisons are presented.