Volkan Esen

Implementation of a Transaction Level Assertion Framework in SystemC

Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL. In this paper we present a prototype implementation of a TL assertion framework using SystemC which is currently the de facto standard for system modeling.

Requirements and Concepts for Transaction Level Assertions

The latest development of hardware design and verification methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction level models are used for early prototyping and as reference models for the verification of their RTL representation. Hence, ensuring their quality is vital for the design process. Assertion based verification (ABV) has already given a good return of investment for RTL designs. We expect the same benefit from leveraging ABV on transaction level; however mapping RTL ABV methodology directly to TL poses severe problems due to the abstraction of time and different model of computation. In this paper we present requirements for TL ABV and introduce a conceptual language for specifying TL properties. We use a simple application example for illustrating the concepts and outline a possible SystemC execution model of the conceptual language.

Execution semantics and formalisms for multi-abstraction TLM assertions

Electronic system level (ESL) reflects the current trend in hardware design and verification towards abstraction levels higher than RTL referred to as transaction level (TL). Raising the abstraction level leads to reduced complexity compared to classical RTL modeling; however, due to this lack of detail, verification of higher level models produces new problems. Assertion based verification (ABV) - a well established RTL methodology - is a good example of this. Temporal relations in RTL properties are specified in terms of clocks that trigger the design. It is not obvious how to specify properties for more abstract, non-clocked models where the notion of lime is annotated as estimated delay values or omitted completely. Since ABV has already shown to be a strong methodology for functional RTL verification, we expect the same benefit for TL by lifting current ABV approaches to a higher level. In this paper we present a prototypic formal framework for specifying TL properties. We focus our work on three TL model views, as defined in the OSCI TLM standard. For each view we describe the model of computation and derive the required operators. Furthermore, we explain the required execution semantics and give some application examples

TLM+ modeling of embedded HW/SW systems

Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-facto standard in todays SoC design, enabling early SW development. However, due to the growing complexity of SoC architectures full system simulations (HW+SW) become a bottleneck reducing this benefit. Hence, it is necessary to develop modeling styles which allow for further abstraction beyond the currently applied TLM methodology. This paper introduces such a modeling style, referred to as TLM+. It enables a higher modeling abstraction through merging hardware dependent driver software at the lowest level with the HW interface. Thus, sequences of HW transactions can be merged to single HW/SW transactions while preserving both the HW architecture and the low-level to high-level SW interfaces. In order to maintain the ability to validate timing-critical paths, a new resource model concept is introduced which compensates the loss of timing information, induced by merging HW transactions. Experimental results show a speed-up of up to 1000x at a timing error of approximately 10%.

Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance

In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM). As part of the ongoing re-work modeling language strategies and the world wide introduction of TLM, a detailed analysis of the impact of description languages, abstraction layers and data types on simulation performance is of high importance. For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, SystemVerilog, and SystemC, using different value representations and coding styles, covering the abstraction levels from functional to behavioral to RTL. This paper presents our evaluation environment and several interesting findings of our analysis. The most important results are as follows: We found that HDL tool/language/abstraction selection of RTL models impacts on the execution speed with a factor of 4.4. We found that Verilog is on average 2times faster than VHDL for RTL models. We found that SystemC results in 10times slower RTL models than HDLs and surprisingly results in 2.6times slower TLM PV models than SystemVerilog. And we found finally that on average over all analyzed aspects SystemVerilog models are executed fastest

The system verification methodology for advanced TLM verification

The IEEE-1800 SystemVerilog [20] system description and verification language integrates dedicated verification features, like constraint random stimulus generation and functional coverage, which are the building blocks of the Universal Verification Methodology (UVM)[3], the emerging standard for electronic systems verification. In this article, we introduce our System Verification Methodology (SVM) as a SystemC library for advanced Transaction Level Modeling (TLM) testbench implementation. As such, we first present SystemC libraries for the support of verification features like functional coverage and constrained random stimulus generation. Thereafter, we introduce the SVM with advanced TLM support based on SystemC and compare it to UVM and related approaches. Finally, we demonstrate the application of our SVM by means of a testbench for a two wheel self-balancing electric vehicle.

Specification Language for Transaction Level Assertions

Transaction level (TL) modeling is the basis of the so called electronic system level that allows development of systems on chip at a quicker pace than with classical RTL approaches. Starting from the specification phase of the product development cycle, TL modeling enables easy architecture exploration and early software co-development. In contrast to RTL, TL models (TLM) are more abstract and do not contain micro-architectural details for instance; the design focus is on high-level control and data flow. Since TLMs are essential at the decision process in early system development and as they can serve as golden reference models for later RTL regression, it is imperative to ensure that they implement the specification correctly. Assertion based verification (ABV) has given a good return of investment in RTL verification, decreasing debug time while preserving the design intent leveraging these benefits on the transaction level for the verification of TLMs requires the adaptation of current ABV approaches to the specific characteristics of these abstract models. In this paper we present an assertion specification language, based on formal definitions, that allows the specification of transaction level properties and their execution in simulation. We derive the language from known ABV languages and extend these by the required TL functionality, and explain how simulation traces of finite length can be checked against properties

A transaction-oriented UVM-based library for verification of analog behavior

The Universal Verification Methodology (UVM) has become a de facto standard in todays functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.

Model reduction techniques for the formal verification of hardware dependent software

Contemporary researches provide many solutions for formally verifying both hardware and software systems. In this paper, we describe the formal verification of assembly programs, which are part of the HW/SW interface in hybrid systems. We have developed several methods to model assembly programs in VHDL in order to verify their functionality. Our discussion will show that, by applying different reduction methods, we managed to formally verify the correctness of iterative algorithms with execution times higher than 6000 clock cycles.

Automatically comparing analog behavior using Earth Mover's Distance

Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verification process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in significantly reduced turnaround times as well as a considerably increased reliability of verification results. The presented concept is motivated by an algorithm that is used in optical pattern recognition and is called Earth Movers Distance. Furthermore, we compare our approach with already existing algorithms, namely Fréchet Distance and Pearson Coefficient, in order to analyze its capability. Finally, we present a case study in which we prove the algorithm by applying it to the results of a mixed-signal simulation at chip-level demonstrating the efficiency of our approach.