Michael Velten

Requirements and Concepts for Transaction Level Assertions

The latest development of hardware design and verification methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction level models are used for early prototyping and as reference models for the verification of their RTL representation. Hence, ensuring their quality is vital for the design process. Assertion based verification (ABV) has already given a good return of investment for RTL designs. We expect the same benefit from leveraging ABV on transaction level; however mapping RTL ABV methodology directly to TL poses severe problems due to the abstraction of time and different model of computation. In this paper we present requirements for TL ABV and introduce a conceptual language for specifying TL properties. We use a simple application example for illustrating the concepts and outline a possible SystemC execution model of the conceptual language.

TLM+ modeling of embedded HW/SW systems

Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-facto standard in todays SoC design, enabling early SW development. However, due to the growing complexity of SoC architectures full system simulations (HW+SW) become a bottleneck reducing this benefit. Hence, it is necessary to develop modeling styles which allow for further abstraction beyond the currently applied TLM methodology. This paper introduces such a modeling style, referred to as TLM+. It enables a higher modeling abstraction through merging hardware dependent driver software at the lowest level with the HW interface. Thus, sequences of HW transactions can be merged to single HW/SW transactions while preserving both the HW architecture and the low-level to high-level SW interfaces. In order to maintain the ability to validate timing-critical paths, a new resource model concept is introduced which compensates the loss of timing information, induced by merging HW transactions. Experimental results show a speed-up of up to 1000x at a timing error of approximately 10%.

Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance

In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM). As part of the ongoing re-work modeling language strategies and the world wide introduction of TLM, a detailed analysis of the impact of description languages, abstraction layers and data types on simulation performance is of high importance. For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, SystemVerilog, and SystemC, using different value representations and coding styles, covering the abstraction levels from functional to behavioral to RTL. This paper presents our evaluation environment and several interesting findings of our analysis. The most important results are as follows: We found that HDL tool/language/abstraction selection of RTL models impacts on the execution speed with a factor of 4.4. We found that Verilog is on average 2times faster than VHDL for RTL models. We found that SystemC results in 10times slower RTL models than HDLs and surprisingly results in 2.6times slower TLM PV models than SystemVerilog. And we found finally that on average over all analyzed aspects SystemVerilog models are executed fastest

Specification Language for Transaction Level Assertions

Transaction level (TL) modeling is the basis of the so called electronic system level that allows development of systems on chip at a quicker pace than with classical RTL approaches. Starting from the specification phase of the product development cycle, TL modeling enables easy architecture exploration and early software co-development. In contrast to RTL, TL models (TLM) are more abstract and do not contain micro-architectural details for instance; the design focus is on high-level control and data flow. Since TLMs are essential at the decision process in early system development and as they can serve as golden reference models for later RTL regression, it is imperative to ensure that they implement the specification correctly. Assertion based verification (ABV) has given a good return of investment in RTL verification, decreasing debug time while preserving the design intent leveraging these benefits on the transaction level for the verification of TLMs requires the adaptation of current ABV approaches to the specific characteristics of these abstract models. In this paper we present an assertion specification language, based on formal definitions, that allows the specification of transaction level properties and their execution in simulation. We derive the language from known ABV languages and extend these by the required TL functionality, and explain how simulation traces of finite length can be checked against properties

Using a dataflow abstracted virtual prototype for HdS-design

The complexity of Hardware-dependent Software (HdS) continuously grows faster than chip complexity since more and more tasks aremoved to software. Clearly, the pressure on the development of new methodologies for early validation of HdS increases as well. Existing methods must be continuously improved and new methods must be developed. This is exemplified with an state-of-the-art Transaction Level (TL) model used for firmware development of a productive wireless communication chip. By discussing the strengths and shortcomings of TL modeling we derive a set of requirements for a future modeling paradigm, which led to the new data flow abstraction approach presented in this paper. Experiments showed that we gain up to 10x performance improvement.

The metamodeling approach to system level synthesis

This paper presents an industry proven Metamodeling based approach to System-Level-Synthesis which is seen as generic design automation strategy above todays implementation levels RTL (for digital) and Schematic Entry (for analog). The approach follows a new synthesis paradigm: The designer develops a simple domain and/or design specific language and a smart tool synthesizing implementation level models according to its needs. The overhead of making both a tool and a model pays off since the tool building is automated by code generation and reuse, both based on Metamodeling techniques. Also the focus on owns demand keeps development costs low. Finally, specification data is utilized. I.e. the domain specific language simplifies to a document structure as a table. This keeps also modeling effort low since specification content is used and no model need to be built. Furthermore, increases design consistency and thus decreases debug time. Using these concepts, single design steps have been speed up to a factor of 20x and implementations of chips (specification-to-tapeout) have been speed up to a factor of 3x.

Metasynthesis for Designing Automotive SoCs

Designing Automotive SoCs requires product specific support of one or more different design targets as different degrees of safety, reliability, very low power, or high current support as well as different design features as multi-core, sensor-on-chip, or system-in-package. Considering that wide design space, its clear that EDA industry that is focusing on generic applicable tools leaves a wide field for automation unsupported. This paper presents a novel approach to system synthesis named Metasynthesis. It proposes a new highly flexible methodology based on synthesizing system synthesis tools. These synthesized tools finally make the synthesis step from a description above implementation level, e.g. requirements, specification, or a domain specific description to implementation level, e.g. C, SystemVerilog-RTL or schematic. The name “Meta”-Synthesis was chosen in the sense of a synthesis tool “beyond” another synthesis tool or as already said a synthesis tool synthesizing another synthesis tool. The term “Meta” also reflects the underlying metamodeling technique. Even if the approach requires additional effort in building the system synthesis tool, it helps to shorten overall design time, since building the tool is highly automated due to the presented Metasynthesis approach. Also the input views are fast to make since they can be kept simple and compact. The Metasynthesis approach was proven so far in over 90 different automotive SoC and other applications gaining productivity improvements of 95% considering single design steps and gaining up to 70% effort reduction for the complete implementation of automotive SoCs. Some designers report, that they generate up to 80% of the chips overall RTL code with synthesized tools.

Model reduction techniques for the formal verification of hardware dependent software

Contemporary researches provide many solutions for formally verifying both hardware and software systems. In this paper, we describe the formal verification of assembly programs, which are part of the HW/SW interface in hybrid systems. We have developed several methods to model assembly programs in VHDL in order to verify their functionality. Our discussion will show that, by applying different reduction methods, we managed to formally verify the correctness of iterative algorithms with execution times higher than 6000 clock cycles.

SystemC as completing pillar in industrial OVM based verification environments

This paper presents a novel TLM verification approach utilizing TLM+ as a reference model and providing a systematic path to RTL simulation as well. The approach is based on SystemC only but follows the established structure on an OVM testbench. Industrial relevant aspects as use of standards, early verification, and re-use of design items are established in this way.

HW/SW Interface

This chapter addresses HW/SW interface implementation and modeling. As introduction, basic concepts regarding HW/SW interfaces on both HW and SW side are presented in detail. The focus is on several aspects of register and bit field read/write access, address mismatch, synchronization, and data alignment. The HW micro-architecture is outlined in block diagrams, the SW code is listed in C-code snippets. As new contributions, data flow abstraction for HW/SW models and consistently derived RTL models, TLM models, and C code by using a template approach are presented.