Wolfgang Thomann

A single-chip 75 GHz/0.35 /spl mu/m SiGe BiCMOS W-CDMA homodyne transceiver for UMTS mobiles

A single-chip, fully-integrated 3G UMTS/W-CDMA transceiver has been implemented in a standard 75-GHz/0.35 /spl mu/m SiGe BiCMOS process for use in FDD mobile terminals. The design comprises two integer-N/fractional-N synthesizers with fully integrated CMOS VCOs, on-chip tuning and PLL, a zero-IF receiver and a direct-conversion transmitter. The zero-IF receiver includes a differential-input, bipolar, low-noise amplifier (2nd LNA), a down-converter with CMOS Gilbert type mixers followed by a low-noise buffer amplifier, an analog active baseband filter of 5th-order with automatic on-chip filter calibration and interleaved with a programmable gain amplifier, and a programmable baseband output buffer. The direct-conversion transmitter includes a 4th-order analog active baseband filter, a bipolar direct modulation up-converter, and a variable gain RF amplifier with >80 dB gain control range, and a 3 dBm power amplifier driver. The transceiver is fully-programmable via two serial 3-wire-bus interfaces.. The device operates at 2.7-3.0 V supply and consumes 35 mA and 53-78 mA, in the receive mode and in the transmit mode, respectively. The transceiver is mounted in a small outline, 40-pin, leadless, 5.5/spl times/6.5 mm/sup 2/ surface mount package and fully complies with ARIB W-CDMA and UMTS standards.

Fully integrated W-CDMA IF-receiver and IF-transmitter including IF-synthesizer and on-chip VCO for UMTS mobiles

A fully integrated Si-bipolar IF-receiver and IF-transmitter with on-chip synthesizer for use in third-generation W-CDMA mobiles is introduced. Both devices incorporate an on-chip IF-synthesizer with on-chip VCO tuning and tank as well as fifth order baseband filters and comply with ARIB W-CDMA and UMTS standards. The devices are mounted in a small outline, 32 pin, leadless surface mount package.

A load-insensitive quad-band GSM/EDGE SiGeC-bipolar power amplifier with a highly efficient low power mode

A load-insensitive fully-integrated quad- band GSM/EDGE radio frequency power amplifier for 824-915 MHz and 1710-1910 MHz has been realized in a 0.35-mum SiGeC-Bipolar technology. The chip integrates a low- and high-band 3-stage power amplifier including a bias-control circuit for power control, band select and mode as well as ramping dependent quiescent currents. The load-insensitive balanced PA architecture delivers for an adjusted output power of 34.5 dBm for all phases of a 3:1 VSWR a low deviation only 1.3 dB. At 3.5 V a saturated output power of 36.7 dBm is achieved at 870 MHz and 34 dBm at 1710 MHz. The respective peak PAE is 52% for low band and 42 % for high-band. The PA features a unique switched low power mode that involves disabling one half of each PA.

An integrated 20 GHz SiGe bipolar differential oscillator with high tuning range

A fully integrated, differential LC oscillator manufactured in Infineons B7HF SiGe bipolar technology with an f/sub T/ and f/sub max/ of 75 GHz is presented. The oscillator features a tank consisting of on-chip stripline inductors and the parasitic capacitances of the oscillator transistors. A tuning range of 14-21.5 GHz over bias current is achieved. The output buffer is inductively coupled to the tank. Total current consumption including the buffer is 13 mA from a 3 V supply at the maximum oscillation frequency of 21.5 GHz. The measured phase-noise at 1 MHz offset is -85 dBc/Hz at a core bias current of 7 mA.

A multi-mode power amplifier for enhanced PAE in back-off operation with load insensitive architecture

A novel multi-mode power amplifier (PA) concept with improved efficiency over a wide range of output power is presented. It incorporates three power back-off modes with enhanced efficiency and provides a high tolerance to load variations in all modes. This approach offers sufficient linearity for high crest factor signals such as WCDMA and EDGE without requiring any predistortion. The conditions for optimum operation of the PA topology, based on power combining of parallel amplifier stages with quadrature hybrids, are derived. The chip is implemented in a 0.35 µm SiGeC-bipolar technology. In GSM operation measurements at 840 MHz yield a peak power of 36.1 dBm at 52.5 % PAE. In back-off WCDMA operation the PA yields, at an average max. power of 27 dBm, a PAE of 37 % and at an average usecase power of 19 dBm a PAE of 27 %. In EDGE operation at 29 dBm a PAE of 27 % and a 3 dB margin to the system linearity specification are achieved.