Markus Zannoth

A fully integrated VCO at 2 GHz

An integrated voltage-controlled oscillator (VCO) at a frequency of 2 GHz is implemented in a f/sub T/= 25 GHz standard bipolar process. The phase noise of the VCO is -136 dBc/Hz at 4.7 MHz frequency offset. The LC-resonator uses vertically coupled on-chip inductors and integrated tuning diodes. Due to the poor performance of integrated resonators on silicon ICs, oscillators with phase noise meeting requirements of wireless applications are difficult to integrate. With fully integrated designs only the standards for cordless phones, for instance DECT, can be achieved. The critical point in the DECT-specification is the emission of the transmitter due to intermodulation in the third adjacent channel, that must be <-47 dBm. This value is measured with an integration bandwidth of 1 MHz centered at the nominal center frequency. With a channel-spacing of 1.728 MHz the third adjacent channel is located 5.184 MHz from the actual transmit channel frequency. The beginning of the integration bandwidth is at an offset frequency of 4.684 MHz related to the nominal frequency of the transmit channel. This is the offset frequency, at which the specification must be met. The resulting noise requirement is -132 dBc/Hz at a offset frequency of 4.684 MHz, when the integration bandwidth and the transmit output power of 25 dBm are taken into account.

A load-insensitive quad-band GSM/EDGE SiGeC-bipolar power amplifier with a highly efficient low power mode

A load-insensitive fully-integrated quad- band GSM/EDGE radio frequency power amplifier for 824-915 MHz and 1710-1910 MHz has been realized in a 0.35-mum SiGeC-Bipolar technology. The chip integrates a low- and high-band 3-stage power amplifier including a bias-control circuit for power control, band select and mode as well as ramping dependent quiescent currents. The load-insensitive balanced PA architecture delivers for an adjusted output power of 34.5 dBm for all phases of a 3:1 VSWR a low deviation only 1.3 dB. At 3.5 V a saturated output power of 36.7 dBm is achieved at 870 MHz and 34 dBm at 1710 MHz. The respective peak PAE is 52% for low band and 42 % for high-band. The PA features a unique switched low power mode that involves disabling one half of each PA.

Outphasing Power Amplifier Design Investigations for 2.5G and 3G Standards

This paper presents investigations on outphasing power amplifier realizations based on a 2-stage 0.35 mum SiGe-bipolar PA design for 850 MHz and 1800 MHz. A Chireix combiner, a 90deg hybrid coupler and a Wilkinson power combiner were designed and all types were characterized in terms of efficiency and linearity for the usage in mobile phone applications.

Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip

In various fields, there is a growing need for electric motor drives and inductive power converters. To achieve better switching behavior and lower EME in inductive switching applications, very precise gate control of the power MOSFETs by the gate driver is required. The driver presented in this paper can operate at voltages up to 60V, and it is able to change the gate current in 10 / 15ns (rise / fall delay) within a range of 20mA to 500mA. Achieved by a class B buffer in the output stage, this enables multiple current changes in a 100ns switching transition. A dip in the output current, caused by parasitic capacitances, is reduced from 80% of the full scale current to 20% by a cascode configuration in the driver output stage. The gate voltage is clamped to 11.5V, with a precise clamping circuit to reduce RDS,on with the full gate current, but without stressing the gate oxide with any over voltage. By fully integrating this concept in 130nm HV-BiCMOS, a reduction in external components for limiting overshoot, stress and EME can be achieved.