Won-Joon Choi

An Integrated Draft 802.11n Compliant MIMO Baseband and MAC Processor

A 3 times 3 MIMO baseband and MAC processor in 0.18 mum 6M CMOS occupies 62.1 mm2 and dissipates (Tx/Rx) 1379/1200mW at 1.8V including ADCs, DACs, and PCI/PCIe PHY. The integrated BB and MAC delivers up to 300Mb/s in 40MHz bandwidth, greater than 150Mb/s TCP throughput best case and a maximum range of 700ft range.

MIMO technology for advanced wireless local area networks

This paper first gives a brief introduction to multiple input multiple output (MIMO) wireless communication systems. Various architectures of MIMO systems and corresponding features are discussed, including those proposed for the IEEE 802.11n standard. The impact on chip area and required data processing rates is then presented.

Circuit implications of MIMO technology for advanced wireless local area networks

This paper first gives a brief introduction to multiple input multiple output (MIMO) wireless communication systems. Various architectures of MIMO systems and corresponding features are discussed, including those proposed for the IEEE 802.11n standards committee. The constraints on RF circuits in a MIMO system are then addressed, as well as the impact of analog impairments on the performance of MIMO systems. Finally, the paper discusses calibration procedures in MIMO systems.

A WLAN SoC for video applications including beamforming and maximum ratio combining

A WLAN SoC for video applications handles IEEE 802.11a/b/g and supports PHY data rates to 108 Mbit/s. The SoC implements two chain maximum ratio combining and beamforming. Video features include a jitter removal system and MPEG-TS packet aggregation. Measured results on the 7.2mm/spl times/7.2mm IC using a 0.18 /spl mu/m CMOS process demonstrate throughput improvements in both RX and TX.