William J. McFarland

An IC for linearizing RF power amplifiers using envelope elimination and restoration

Efficient power amplifiers (PAs) are desirable because power amplifiers typically dominate the power consumed in portable radio devices. Cellular systems such as the advanced mobile phone system (AMPS) employ modulation schemes that generate constant amplitude RF outputs to use efficient but nonlinear PAs. Modern digital communication standards such as the North American dual-mode cellular (NADC) system require nonconstant amplitude RF outputs to maximize frequency spectral usage, and therefore require linear PAs. The traditional approach to linear RF power amplification is to back-off the output power of a PA until its distortion is reduced to an acceptable level. Power back-off can lead to significant reduction in output power and efficiency. The envelope elimination and restoration (EER) system is an alternative to power back-off, to simultaneously achieve efficiency and linearity in RF PAs.

A 2.5-V, 1-W monolithic CMOS RF power amplifier

A monolithic CMOS RF power amplifier has been designed and fabricated in a standard 0.8-/spl mu/m CMOS technology and shown to provide l-W of output power at 824-849 MHz to a 50-ohm load from a single 2.5-V supply. The prototype amplifier has a measured drain efficiency of 62%, an overall power-added efficiency of 42%, a power gain of 25 dB, and a total die area of 1.5 mm/sup 2/.

An image-rejecting mixer and vector filter with 55-dB image rejection over process, temperature, and transistor mismatch

This paper describes an image-rejecting mixer and vector filter for use in radio systems with channel bandwidths in the range of 1 MHz. The circuit replaces the SAW filter and second downconverter commonly used in this style of radio. Because the output of the circuit is at an IF of 5 MHz, traditional demodulation methods including limiting and FM discrimination can still be used. The circuit is based on a quadrature mixer that guarantees good performance despite device mismatches and process variation. The circuit consumes 29 mA at 3.3 V,and achieves better than 55-dB image rejection despite device mismatches and process variation and is implemented in a single-poly triple metal 0.5 /spl mu/m CMOS process with linear capacitor implants. The circuit is designed for input signals from 125 to 250 MHz. Input referred voltage noise is 900 /spl mu/Vrms. The in-band IP3 is 18 dBm. By changing an external reference frequency, the passband width of the filter can be varied from 3 to 0.5 MHz.

1-Gword/s pseudorandom word generator

An integrated circuit that generates 16-bit pseudorandom words at up to 1 Gword/s is presented. The concept of a pseudorandom word sequence is introduced. The pseudorandom words shown have excellent properties for testing serial or parallel components and data links. If serialized, the words would form a pseudorandom bit sequence with a potential maximum serial bit rate of 16 Gb/s. The circuit was implemented in an advanced silicon bipolar process with an f/sub T/ of 10 GHz. The chip includes 16 output drivers, with adjustable amplitude and offset, capable of driving 25- Omega loads with 0.8-V swings and 400-ps rise times. Total chip dissipation is under 4 W on a 2-mm*2-mm die. >

A WLAN SoC for video applications including beamforming and maximum ratio combining

A WLAN SoC for video applications handles IEEE 802.11a/b/g and supports PHY data rates to 108 Mbit/s. The SoC implements two chain maximum ratio combining and beamforming. Video features include a jitter removal system and MPEG-TS packet aggregation. Measured results on the 7.2mm/spl times/7.2mm IC using a 0.18 /spl mu/m CMOS process demonstrate throughput improvements in both RX and TX.