Won-Mook Kang

High-gain complementary metal-oxide-semiconductor inverter based on multi-layer WSe2 field effect transistors without doping

A high-gain complementary metal-oxide-semiconductor (CMOS) logic inverter was implemented by fabricating p- and n-type field effect transistors (FETs) based on multi-layer WSe2 on the same wafer. Au as a high work-function metal is contacted to WSe2 for the source/drain of the p-type FET. The n-type FET has an Al electrode contacted to WSe2 for the source/drain. Both FETs were designed to have similar on-current densities (>10−7 A μm−1) and high on/off current ratios (>106). The inverter shows excellent switching characteristics including relatively high voltage gains (>25) and high noise margins (>0.9) in the range of supply voltage from 2 V to 8 V. This work has a great significance in the realization of a CMOS logic gate based on WSe2 without an additional doping scheme.

Elimination of the gate and drain bias stresses in I–V characteristics of WSe2 FETs by using dual channel pulse measurement

Intrinsic transfer and output characteristics of WSe2 field effect transistors are obtained by adopting the dual channel pulsed I–V measurement. Due to the DC gate bias stress during the measurement, a large hysteresis is observed and increased with increasing the sweeping range of the gate bias in the transfer curves. In addition, as a drain bias increases, the drain bias stress during the measurement induces the threshold voltage shift. The output curves measured by a DC method are significantly affected by the drain bias sweeping direction and the previous measurement, which leads to a large error in the analysis. By using the dual channel pulsed I–V measurement with a short turn-on time (10−4 s), a long turn-off time (1 s), and a base voltage (gate and drain bias during turn-off time) of 0 V, hysteretic behaviors caused by the gate bias stress and threshold voltage shift due to the drain bias stress in transfer curves are eliminated. The effect of the drain bias sweeping direction and the previous mea...

Emerging memory technologies for neuromorphic computing

In this paper, we reviewed the recent trends on neuromorphic computing using emerging memory technologies. Two representative learning algorithms used to implement a hardware-based neural network are described as a bio-inspired learning algorithm and software-based learning algorithm, in particular back-propagation. The requirements of the synaptic device to apply each algorithm were analyzed. Then, we reviewed the research trends of synaptic devices to implement an artificial neural network.

A Split-Gate Positive Feedback Device With an Integrate-and-Fire Capability for a High-Density Low-Power Neuron Circuit

Hardware-based spiking neural networks (SNNs) to mimic biological neurons have been reported. However, conventional neuron circuits in SNNs have a large area and high power consumption. In this work, a split-gate floating-body positive feedback (PF) device with a charge trapping capability is proposed as a new neuron device that imitates the integrate-and-fire function. Because of the PF characteristic, the subthreshold swing (SS) of the device is less than 0.04 mV/dec. The super-steep SS of the device leads to a low energy consumption of ∼0.25 pJ/spike for a neuron circuit (PF neuron) with the PF device, which is ∼100 times smaller than that of a conventional neuron circuit. The charge storage properties of the device mimic the integrate function of biological neurons without a large membrane capacitor, reducing the PF neuron area by about 17 times compared to that of a conventional neuron. We demonstrate the successful operation of a dense multiple PF neuron system with reset and lateral inhibition using a common self-controller in a neuron layer through simulation. With the multiple PF neuron system and the synapse array, on-line unsupervised pattern learning and recognition are successfully performed to demonstrate the feasibility of our PF device in a neural network.

Comparison of DC, fast I-V, and pulsed I-V measurement method in multi-layer WSe 2 field effect transistors

Transfer characteristics of the WSe2 field effect transistors are measured by the dc, fast I-V, and pulsed I-V methods. In the dc measurement, large hysteresis is observed. In the fast I-V measurement, less hysteresis is obtained with a faster sweeping rate, however, the hysteresis is still not negligible. By applying the pulsed I-V method with short on time (~10-4 s), and long off time (~1 s), the hysteresis-free characteristics of WSe2 FETs are obtained, and noticeably enhanced mobility (~160 cm2/V·s) is observed.

Temperature effects on current-voltage and low frequency noise characteristics of multilayer WSe 2 FETs

We investigates the temperature effect on current-voltage and low frequency noise of multilayer WSe2 FETs. The field effect mobility (μFE), Ion/Ioff, subthreshold slope (SS) and hysteresis were deteriorated as the temperature increases. It is because of enhanced phonon scattering and increase of thermally generated carrier density. From the dependence of noise power spectral density of drain current, carrier mobility fluctuation is considered as a dominant low frequency noise mechanism. The extracted Hooges parameter slightly increased with temperature increase. It is because of enhanced phonon scattering.